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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2021 Luo Jia (HUST IoT Security Lab)
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* Add specific clock configuration (HSE, LSE) for this board here */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23#include "periph_cpu.h"
24#include "clk_conf.h"
25#include "cfg_rtt_default.h"
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
36static const timer_conf_t timer_config[] = {
37 {
38 .dev = TIM5,
39 .max = 0xffffffff,
40 .rcc_mask = RCC_APB1ENR1_TIM5EN,
41 .bus = APB1,
42 .irqn = TIM5_IRQn
43 }
44};
45
46#define TIMER_0_ISR isr_tim5
47
48#define TIMER_NUMOF ARRAY_SIZE(timer_config)
50
56static const uart_conf_t uart_config[] = {
57 {
58 .dev = USART1,
59 .rcc_mask = RCC_APB2ENR_USART1EN,
60 .rx_pin = GPIO_PIN(PORT_A, 10),
61 .tx_pin = GPIO_PIN(PORT_A, 9),
62 .rx_af = GPIO_AF7,
63 .tx_af = GPIO_AF7,
64 .bus = APB2,
65 .irqn = USART1_IRQn,
66 .type = STM32_USART,
67 .clk_src = 0, /* Use APB clock */
68#ifdef UART_USE_DMA
69 .dma_stream = 6,
70 .dma_chan = 4
71#endif
72 }
73};
74
75#define UART_0_ISR (isr_usart1)
76
77#define UART_NUMOF ARRAY_SIZE(uart_config)
79
80#ifdef __cplusplus
81}
82#endif
83
@ PORT_A
port A
Definition periph_cpu.h:43
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
Timer device configuration.
Definition periph_cpu.h:260
UART device configuration.
Definition periph_cpu.h:214