Loading...
Searching...
No Matches
cc2538_sys_ctrl.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2014 Loci Controls Inc.
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#include "cc2538.h"
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
28typedef struct {
29
33 union {
35 struct {
48 } CLOCK_CTRLbits;
49 } cc2538_sys_ctrl_clk_ctrl;
50
54 union {
56 struct {
61 cc2538_reg_t OSC : 1;
72 } CLOCK_STAbits;
73 } cc2538_sys_ctrl_clk_sta;
74
83
87 union {
89 struct {
93 } RCGCUARTbits;
94 } cc2538_sys_ctrl_unnamed1;
95
99 union {
101 struct {
102 cc2538_reg_t UART0 : 1;
103 cc2538_reg_t UART1 : 1;
105 } SCGCUARTbits;
106 } cc2538_sys_ctrl_unnamed2;
107
111 union {
113 struct {
114 cc2538_reg_t UART0 : 1;
115 cc2538_reg_t UART1 : 1;
117 } DCGCUARTbits;
118 } cc2538_sys_ctrl_unnamed3;
119
144
145#define SYS_CTRL ( (cc2538_sys_ctrl_t*)0x400d2000 )
146
150#define sys_clock_freq() ((uint32_t)\
151 (SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC ? \
152 RCOSC16M_FREQ : XOSC32M_FREQ) >> \
153 SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.SYS_DIV)
154
155#ifdef __cplusplus
156} /* end extern "C" */
157#endif
158
CC2538 MCU interrupt and register definitions.
volatile uint32_t cc2538_reg_t
Least-significant 32 bits of the IEEE address.
Definition cc2538.h:120
System Control component registers.
cc2538_reg_t IO_DIV
I/O clock rate setting.
cc2538_reg_t RESERVED12[4]
Reserved bits.
cc2538_reg_t PWRDBG
Power debug register.
cc2538_reg_t IWE
This register controls interrupt wake-up.
cc2538_reg_t SCGCSSI
Module clocks for SSI[1:0] when the CPU is insSleep mode.
cc2538_reg_t RESERVED4
Reserved bits.
cc2538_reg_t RST
Last source of reset.
cc2538_reg_t SCGCUART
Module clocks for UART[1:0] when the CPU is in sleep mode.
cc2538_reg_t OSC32K
32-kHz clock oscillator selection
cc2538_reg_t RESERVED13[3]
Reserved bits.
cc2538_reg_t SRGPT
Reset for GPT[3:0].
cc2538_reg_t RCGCSEC
Module clocks for the security module when the CPU is in active (run) mode.
cc2538_reg_t SCGCRFC
This register defines the module clocks for RF CORE when the CPU is in sleep mode.
cc2538_reg_t RESERVED
Reserved bits.
cc2538_reg_t RESERVED10[5]
Reserved bits.
cc2538_reg_t DCGCSSI
Module clocks for SSI[1:0] when the CPU is in PM0.
cc2538_reg_t CLOCK_STA
Clock status register.
cc2538_reg_t RESERVED5
Reserved bits.
cc2538_reg_t OSC32K_CADIS
Disable calibration 32-kHz RC oscillator.
cc2538_reg_t RESERVED7
Reserved bits.
cc2538_reg_t UART0
Enable UART0 clock in active (run) mode.
cc2538_reg_t DCGCRFC
This register defines the module clocks for RF CORE when the CPU is in PM0.
cc2538_reg_t EMUOVR
This register defines the emulator override controls for power mode and peripheral clock gate.
cc2538_reg_t SCGCGPT
Module clocks for GPT[3:0] when the CPU is in sleep mode.
cc2538_reg_t AMP_DET
Amplitude detector of XOSC during power up.
cc2538_reg_t HSOSC_STB
HSOSC stable status.
cc2538_reg_t SRSSI
Reset for SSI[1:0].
cc2538_reg_t SRI2C
Reset for I2C.
cc2538_reg_t RCGCRFC
This register defines the module clocks for RF CORE when the CPU is in active (run) mode.
cc2538_reg_t RESERVED6
Reserved bits.
cc2538_reg_t RESERVED8
Reserved bits.
cc2538_reg_t CLD
This register controls the clock loss detection feature.
cc2538_reg_t RCGCSSI
Module clocks for SSI[1:0] when the CPU is in active (run) mode.
cc2538_reg_t DCGCUART
Module clocks for UART[1:0] when the CPU is in PM0.
cc2538_reg_t SYNC_32K
32-kHz clock source synced to undivided system clock (16 or 32 MHz)
cc2538_reg_t PMCTL
Power mode.
cc2538_reg_t SRUART
Reset for UART[1:0].
cc2538_reg_t RESERVED11[2]
Reserved bits.
cc2538_reg_t DCGCI2C
Module clocks for I2C when the CPU is in PM0.
cc2538_reg_t RCGCGPT
Module clocks for GPT[3:0] when the CPU is in active (run) mode.
cc2538_reg_t RESERVED1
Reserved bits.
cc2538_reg_t SOURCE_CHANGE
System clock source change.
cc2538_reg_t RESERVED2
Reserved bits.
cc2538_reg_t DCGCGPT
Module clocks for GPT[3:0] when the CPU is in PM0.
cc2538_reg_t SCGCI2C
Module clocks for I2C when the CPU is in sleep mode.
cc2538_reg_t CLOCK_CTRL
Clock control register.
cc2538_reg_t SCGCSEC
Module clocks for the security module when the CPU is in sleep mode.
cc2538_reg_t RESERVED9
Reserved bits.
cc2538_reg_t OSC32K_CALDIS
Disable calibration 32-kHz RC oscillator.
cc2538_reg_t DCGCSEC
Module clocks for the security module when the CPU is in PM0.
cc2538_reg_t XOSC_STB
XOSC stable status.
cc2538_reg_t I_MAP
This register selects which interrupt map to be used.
cc2538_reg_t OSC_PD
Oscillator power-down.
cc2538_reg_t RESERVED3
Reserved bits.
cc2538_reg_t UART1
Enable UART1 clock in active (run) mode.
cc2538_reg_t SYS_DIV
System clock rate setting.
cc2538_reg_t OSC
System clock oscillator selection.
cc2538_reg_t SRSEC
Reset for the security module.
cc2538_reg_t RCGCUART
Module clocks for UART[1:0] when the CPU is in active (run) mode.
cc2538_reg_t RCGCI2C
Module clocks for I2C when the CPU is in active (run) mode.
cc2538_reg_t SRCRC
CRC on state retention.