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cfg_usb_otg_fs.h
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1/*
2 * SPDX-FileCopyrightText: 2019 Koen Zandberg
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
28#define DWC2_USB_OTG_FS_ENABLED
29
34 {
35 .periph = USB_OTG_FS_PERIPH_BASE,
36 .type = DWC2_USB_OTG_FS,
38 .rcc_mask = RCC_AHB2ENR_OTGFSEN,
39 .irqn = OTG_FS_IRQn,
40 .ahb = AHB2,
41 .dm = GPIO_PIN(PORT_A, 11),
42 .dp = GPIO_PIN(PORT_A, 12),
43 .af = GPIO_AF10,
44 }
45};
46
50#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
51
52#ifdef __cplusplus
53}
54#endif
55
@ PORT_A
port A
Definition periph_cpu.h:43
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
@ GPIO_AF10
use alternate function 10
Definition cpu_gpio.h:112
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_BUILTIN
on-chip FS PHY
@ DWC2_USB_OTG_FS
Full speed peripheral.