27#include "periph_cpu.h"
37#define DWC2_USB_OTG_HS_ENABLED
39#ifndef USBPHYC_TUNE_VALUE
53#define USBPHYC_TUNE_VALUE 0x00000f13U
61 .periph = USB_OTG_HS_PERIPH_BASE,
64 .rcc_mask = RCC_AHB1ENR_OTGHSEN,
77#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define USBPHYC_TUNE_VALUE
Default value of USBPHYC tuning control register.
@ GPIO_AF10
use alternate function 10
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_UTMI
UTMI for internal HS PHY.
@ DWC2_USB_OTG_HS
High speed peripheral.