Clock configuration for the RP2350. More...

Detailed Description

Clock configuration for the RP2350.

Author: Tom Hert git@a.nosp@m.nnsa.nosp@m.nn.eu

Definition in file clock_conf.h.

#include "RP2350.h"
#include "macros/units.h"

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#define	XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0u
	1-15 MHz range

#define	XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ 0xaa1u
	10-30 MHz range

#define	XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ 0xaa2u
	25-60 MHz range

#define	XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ 0xaa3u
	40-100 MHz range

#define	XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1eu
	Disable the XOSC.

#define	XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfabu
	Enable the XOSC.

#define	XOSC_CTRL_ENABLE_LSB 12u
	LSB of the enable bit.

#define	XOSC_STATUS_STABLE_BITS 0x80000000u
	Stable bit in the XOSC status register.

#define	XOSC_HZ MHZ(12u)
	Default crystal frequency is 12 MHz.

#define	PLL_REF_DIV 2u
	Reference divider for the PLL, set to 2 as per hardware manual.

#define	PLL_VCO_FREQ 750000000u
	VCO frequency for the PLL, set to 750 MHz as per hardware manual.

#define	PLL_PD1 6u
	Post divider 1 for the PLL, set to 6 as per hardware manual.

#define	PLL_PD2 2u
	Post divider 2 for the PLL, set to 2 as per hardware manual.

#define	PLL_PWR_PD_BITS 0x00000001u
	Power down bits for the PLL.

#define	PLL_PWR_VCOPD_BITS 0x00000020u
	VCO power down bits for the PLL.

#define	PLL_CS_LOCK_BITS 0x80000000u
	Lock bit in the PLL control status register.

#define	PLL_PRIM_POSTDIV1_LSB 16u
	LSB of the post divider 1 in the PLL primary register.

#define	PLL_PRIM_POSTDIV2_LSB 12u
	LSB of the post divider 2 in the PLL primary register.

#define	PLL_PWR_POSTDIVPD_BITS 0x00000008u
	Post divider power down bits for the PLL.

#define	CLK_PERI_CTRL_ENABLE_BIT (1u << 11u)
	Enable bit for the peripheral clock control register.

#define	CPUFREQ 125000000u
	Default CPU frequency in Hz, set to 125 MHz as per hardware manual.

#define	CLOCK_XOSC_MAX MHZ(15u)
	Maximum crystal frequency.

#define	CLOCK_XOSC_MIN MHZ(5u)
	Minimum crystal frequency.

#define	CLOCK_XOSC (XOSC_HZ)
	Crystal frequency.

#define	PLL_POSTDIV_MIN 1u
	Minimum value of the post PLL clock divers.

#define	PLL_POSTDIV_MAX 7u
	Maximum value of the post PLL clock divers.

#define	PLL_VCO_FEEDBACK_SCALE_MIN 16u
	Minimum value of the PLL VCO feedback scaler.

#define	PLL_VCO_FEEDBACK_SCALE_MAX 320u
	Maximum value of the PLL VCO feedback scaler.

#define	PLL_REF_DIV_MIN 1u
	Minimum value of the clock divider applied before feeding in the reference clock into the PLL.

#define	PLL_REF_DIV_MAX 1u
	Minimum value of the clock divider applied before feeding in the reference clock into the PLL.

#define	PLL_FEEDBACK_DIVIDER_VALUE 125u
	PLL feedback divider value, set to 125 as per hardware manual.

#define	CLK_SYS_PERI_CTRL_ENABLE_BIT (1u << 0u)
	Enable bit for the system clock control register to select the peripheral clock.

#define	CLK_SYS_SELECTED_PERI_FIELD_VALUE 2u
	Selected field value for the system clock control register to select the peripheral clock.

#define	CLOCK_CORECLOCK MHZ(12u)
	RIOT core clock frequency defined as the CPU frequency.

#define	PDIV ((PLL_PD1 << PLL_PRIM_POSTDIV1_LSB) \| (PLL_PD2 << PLL_PRIM_POSTDIV2_LSB))
	Post divider for the PLL, calculated based on the post divider values.

#define	FBDIV ((PLL_VCO_FREQ / XOSC_HZ) / PLL_REF_DIV)
	Feedback divider for the PLL, calculated based on the VCO frequency and reference clock frequency.

void	xosc_start (void)
	Configures the Crystal to run.

void	xosc_stop (void)
	Stop the crystal.

void	xosc_sleep (uint32_t milliseconds)
	Sleep for a given time in milliseconds.

void	clock_reset (void)
	Reset the clock system.

void	cpu_clock_init (void)
	Configures the XOSC and then sets CLK_SYS, PLL_SYS and CLK_PERI to it.

Macro Definition Documentation

◆ CLK_PERI_CTRL_ENABLE_BIT

#define CLK_PERI_CTRL_ENABLE_BIT (1u << 11u)

Enable bit for the peripheral clock control register.

Definition at line 63 of file clock_conf.h.

◆ CLK_SYS_PERI_CTRL_ENABLE_BIT

#define CLK_SYS_PERI_CTRL_ENABLE_BIT (1u << 0u)

Enable bit for the system clock control register to select the peripheral clock.

Definition at line 90 of file clock_conf.h.

◆ CLK_SYS_SELECTED_PERI_FIELD_VALUE

#define CLK_SYS_SELECTED_PERI_FIELD_VALUE 2u

Selected field value for the system clock control register to select the peripheral clock.

Definition at line 93 of file clock_conf.h.

◆ CLOCK_CORECLOCK

#define CLOCK_CORECLOCK MHZ(12u)

RIOT core clock frequency defined as the CPU frequency.

Definition at line 95 of file clock_conf.h.

◆ CLOCK_XOSC

#define CLOCK_XOSC (XOSC_HZ)

Crystal frequency.

Definition at line 71 of file clock_conf.h.

◆ CLOCK_XOSC_MAX

#define CLOCK_XOSC_MAX MHZ(15u)

Maximum crystal frequency.

Definition at line 67 of file clock_conf.h.

◆ CLOCK_XOSC_MIN

#define CLOCK_XOSC_MIN MHZ(5u)

Minimum crystal frequency.

Definition at line 69 of file clock_conf.h.

◆ CPUFREQ

#define CPUFREQ 125000000u

Default CPU frequency in Hz, set to 125 MHz as per hardware manual.

Definition at line 65 of file clock_conf.h.

◆ FBDIV

#define FBDIV ((PLL_VCO_FREQ / XOSC_HZ) / PLL_REF_DIV)

Feedback divider for the PLL, calculated based on the VCO frequency and reference clock frequency.

Definition at line 115 of file clock_conf.h.

◆ PDIV

#define PDIV ((PLL_PD1 << PLL_PRIM_POSTDIV1_LSB) | (PLL_PD2 << PLL_PRIM_POSTDIV2_LSB))

Post divider for the PLL, calculated based on the post divider values.

Definition at line 112 of file clock_conf.h.

◆ PLL_CS_LOCK_BITS

#define PLL_CS_LOCK_BITS 0x80000000u

Lock bit in the PLL control status register.

Definition at line 55 of file clock_conf.h.

◆ PLL_FEEDBACK_DIVIDER_VALUE

#define PLL_FEEDBACK_DIVIDER_VALUE 125u

PLL feedback divider value, set to 125 as per hardware manual.

Definition at line 87 of file clock_conf.h.

◆ PLL_PD1

#define PLL_PD1 6u

Post divider 1 for the PLL, set to 6 as per hardware manual.

Definition at line 47 of file clock_conf.h.

◆ PLL_PD2

#define PLL_PD2 2u

Post divider 2 for the PLL, set to 2 as per hardware manual.

Definition at line 49 of file clock_conf.h.

◆ PLL_POSTDIV_MAX

#define PLL_POSTDIV_MAX 7u

Maximum value of the post PLL clock divers.

Definition at line 75 of file clock_conf.h.

◆ PLL_POSTDIV_MIN

#define PLL_POSTDIV_MIN 1u

Minimum value of the post PLL clock divers.

Definition at line 73 of file clock_conf.h.

◆ PLL_PRIM_POSTDIV1_LSB

#define PLL_PRIM_POSTDIV1_LSB 16u

LSB of the post divider 1 in the PLL primary register.

Definition at line 57 of file clock_conf.h.

◆ PLL_PRIM_POSTDIV2_LSB

#define PLL_PRIM_POSTDIV2_LSB 12u

LSB of the post divider 2 in the PLL primary register.

Definition at line 59 of file clock_conf.h.

◆ PLL_PWR_PD_BITS

#define PLL_PWR_PD_BITS 0x00000001u

Power down bits for the PLL.

Definition at line 51 of file clock_conf.h.

◆ PLL_PWR_POSTDIVPD_BITS

#define PLL_PWR_POSTDIVPD_BITS 0x00000008u

Post divider power down bits for the PLL.

Definition at line 61 of file clock_conf.h.

◆ PLL_PWR_VCOPD_BITS

#define PLL_PWR_VCOPD_BITS 0x00000020u

VCO power down bits for the PLL.

Definition at line 53 of file clock_conf.h.

◆ PLL_REF_DIV

#define PLL_REF_DIV 2u

Reference divider for the PLL, set to 2 as per hardware manual.

Definition at line 43 of file clock_conf.h.

◆ PLL_REF_DIV_MAX

#define PLL_REF_DIV_MAX 1u

Minimum value of the clock divider applied before feeding in the reference clock into the PLL.

Definition at line 85 of file clock_conf.h.

◆ PLL_REF_DIV_MIN

#define PLL_REF_DIV_MIN 1u

Minimum value of the clock divider applied before feeding in the reference clock into the PLL.

Definition at line 82 of file clock_conf.h.

◆ PLL_VCO_FEEDBACK_SCALE_MAX

#define PLL_VCO_FEEDBACK_SCALE_MAX 320u

Maximum value of the PLL VCO feedback scaler.

Definition at line 79 of file clock_conf.h.

◆ PLL_VCO_FEEDBACK_SCALE_MIN

#define PLL_VCO_FEEDBACK_SCALE_MIN 16u

Minimum value of the PLL VCO feedback scaler.

Definition at line 77 of file clock_conf.h.

◆ PLL_VCO_FREQ

#define PLL_VCO_FREQ 750000000u

VCO frequency for the PLL, set to 750 MHz as per hardware manual.

Definition at line 45 of file clock_conf.h.

◆ XOSC_CTRL_ENABLE_LSB

#define XOSC_CTRL_ENABLE_LSB 12u

LSB of the enable bit.

Definition at line 37 of file clock_conf.h.

◆ XOSC_CTRL_ENABLE_VALUE_DISABLE

#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1eu

Disable the XOSC.

Definition at line 33 of file clock_conf.h.

◆ XOSC_CTRL_ENABLE_VALUE_ENABLE

#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfabu

Enable the XOSC.

Definition at line 35 of file clock_conf.h.

◆ XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ

#define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ 0xaa1u

10-30 MHz range

Definition at line 27 of file clock_conf.h.

◆ XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ

#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0u

1-15 MHz range

See also: hardware/regs/xosc.h and chapter 8.2.8

Definition at line 25 of file clock_conf.h.

◆ XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ

#define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ 0xaa2u

25-60 MHz range

Definition at line 29 of file clock_conf.h.

◆ XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ

#define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ 0xaa3u

40-100 MHz range

Definition at line 31 of file clock_conf.h.

◆ XOSC_HZ

#define XOSC_HZ MHZ(12u)

Default crystal frequency is 12 MHz.

Definition at line 41 of file clock_conf.h.

◆ XOSC_STATUS_STABLE_BITS

#define XOSC_STATUS_STABLE_BITS 0x80000000u

Stable bit in the XOSC status register.

Definition at line 39 of file clock_conf.h.

Function Documentation

◆ clock_reset()

void clock_reset ( void )

Reset the clock system.

This function resets the clock system to a known state. It is recommended to call this function before configuring the clock system.

◆ cpu_clock_init()

void cpu_clock_init ( void )

Configures the XOSC and then sets CLK_SYS, PLL_SYS and CLK_PERI to it.

Precondition: Make sure to call clock_reset() before this function to reset the clock system

See also: RP2350 Docs Chapter 8, mostly 8.2 for more details

◆ xosc_sleep()

void xosc_sleep ( uint32_t milliseconds )

Sleep for a given time in milliseconds.

Parameters

milliseconds The time to sleep in milliseconds.

◆ xosc_start()

void xosc_start ( void )

Configures the Crystal to run.

Note: The reference hardware manual suggests to use a 12 MHz crystal, which we use by default.