Loading...
Searching...
No Matches
context_frame.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2017, 2019 JP Bonn, Ken Rabold
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
20
21#if !defined(__ASSEMBLER__)
22#include <stdint.h>
23#endif /* __ASSEMBLER__ */
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#if !defined(__ASSEMBLER__)
30
40 /* Callee saved registers */
41 uint32_t s0;
42 uint32_t s1;
43 uint32_t s2;
44 uint32_t s3;
45 uint32_t s4;
46 uint32_t s5;
47 uint32_t s6;
48 uint32_t s7;
49 uint32_t s8;
50 uint32_t s9;
51 uint32_t s10;
52 uint32_t s11;
53 /* Caller saved registers */
54 uint32_t ra;
55 uint32_t t0;
56 uint32_t t1;
57 uint32_t t2;
58 uint32_t t3;
59 uint32_t t4;
60 uint32_t t5;
61 uint32_t t6;
62 uint32_t a0;
63 uint32_t a1;
64 uint32_t a2;
65 uint32_t a3;
66 uint32_t a4;
67 uint32_t a5;
68 uint32_t a6;
69 uint32_t a7;
70 /* Saved PC for return from ISR */
71 uint32_t pc;
72 uint32_t pad[3];
73};
74
75#endif /* __ASSEMBLER__ */
76
81/* These values are checked for correctness in context_frame.c */
82#define s0_OFFSET 0
83#define s1_OFFSET 4
84#define s2_OFFSET 8
85#define s3_OFFSET 12
86#define s4_OFFSET 16
87#define s5_OFFSET 20
88#define s6_OFFSET 24
89#define s7_OFFSET 28
90#define s8_OFFSET 32
91#define s9_OFFSET 36
92#define s10_OFFSET 40
93#define s11_OFFSET 44
94#define ra_OFFSET 48
95#define t0_OFFSET 52
96#define t1_OFFSET 56
97#define t2_OFFSET 60
98#define t3_OFFSET 64
99#define t4_OFFSET 68
100#define t5_OFFSET 72
101#define t6_OFFSET 76
102#define a0_OFFSET 80
103#define a1_OFFSET 84
104#define a2_OFFSET 88
105#define a3_OFFSET 92
106#define a4_OFFSET 96
107#define a5_OFFSET 100
108#define a6_OFFSET 104
109#define a7_OFFSET 108
110#define pc_OFFSET 112
111#define pad_OFFSET 116
113
117#define CONTEXT_FRAME_SIZE (pad_OFFSET + 12)
118
122#define SP_OFFSET_IN_THREAD 0
123
124#ifdef __cplusplus
125}
126#endif
127
Stores the registers and PC for a context switch.
uint32_t s9
s9 register
uint32_t s6
s6 register
uint32_t t6
t6 register
uint32_t a2
a2 register
uint32_t s5
s5 register
uint32_t s1
s1 register
uint32_t s11
s11 register
uint32_t s2
s2 register
uint32_t t5
t5 register
uint32_t a0
a0 register
uint32_t a3
a3 register
uint32_t s3
s3 register
uint32_t s7
s7 register
uint32_t t0
t0 register
uint32_t pc
program counter
uint32_t t4
t4 register
uint32_t t2
t2 register
uint32_t ra
ra register
uint32_t a6
a6 register
uint32_t s0
s0 register
uint32_t a5
a5 register
uint32_t a4
a4 register
uint32_t a7
a7 register
uint32_t s10
s10 register
uint32_t t3
t3 register
uint32_t pad[3]
padding to maintain 16 byte alignment
uint32_t s8
s8 register
uint32_t s4
s4 register
uint32_t a1
a1 register
uint32_t t1
t1 register