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cpu.h
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1/*
2 * Copyright (C) 2014-2015 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
31
32#include "irq.h"
33#include "sched.h"
34#include "thread.h"
35#include "cpu_conf.h" /* IWYU pragma: export */
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
48#define STACK_CANARY_WORD (0xE7FEE7FEu)
49
56#define PROVIDES_PM_SET_LOWEST
57
64#define CORTEXM_SCB_CPACR_FPU_ACCESS_FULL (0x00f00000)
65
80void cortexm_init(void);
81
91static inline void cortexm_init_fpu(void)
92{
93 /* initialize the FPU on Cortex-M4F CPUs */
94#if (defined(CPU_CORE_CORTEX_M33) || defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)) && defined(MODULE_CORTEXM_FPU)
95 /* give full access to the FPU */
96 SCB->CPACR |= (uint32_t)CORTEXM_SCB_CPACR_FPU_ACCESS_FULL;
97#endif
98}
99
100#if defined(CPU_CORTEXM_INIT_SUBFUNCTIONS) || defined(DOXYGEN)
101
112
123
124#endif /* defined(CPU_CORTEXM_INIT_SUBFUNCTIONS) || defined(DOXYGEN) */
125
131static inline uintptr_t cpu_get_caller_pc(void)
132{
133 uintptr_t lr_ptr;
134 __asm__ __volatile__("mov %0, lr" : "=r"(lr_ptr));
135 return lr_ptr;
136}
137
144static inline void cortexm_sleep_until_event(void)
145{
146 __WFE();
147}
148
154static inline void cortexm_sleep(int deep)
155{
156 if (deep) {
157 SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk);
158 }
159 else {
160 SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
161 }
162
163 /* ensure that all memory accesses have completed and trigger sleeping */
164 unsigned state = irq_disable();
165 __DSB();
166 __WFI();
167 /* Some CPUs require an ISB after WFI to work around silicon bugs */
168#if CORTEXM_ISB_REQUIRED_AFTER_WFI
169 __ISB();
170#endif
171 irq_restore(state);
172}
173
179static inline void cortexm_isr_end(void)
180{
183 }
184}
185
193static inline void cpu_jump_to_image(uint32_t image_address)
194{
195 /* On Cortex-M platforms, the flash begins with:
196 *
197 * 1. 4 byte pointer to stack to be used at startup
198 * 2. 4 byte pointer to the reset vector function
199 *
200 * On powerup, the CPU sets the stack pointer and starts executing the
201 * reset vector.
202 *
203 * We're doing the same here, but we'd like to start at image_address.
204 *
205 * This function must be called while executing from MSP (Master Stack
206 * Pointer).
207 */
208
209 /* set MSP */
210 __set_MSP(*(uint32_t*)image_address);
211
212 /* skip stack pointer */
213 image_address += 4;
214
215 /* load the images reset_vector address */
216 uint32_t destination_address = *(uint32_t*)image_address;
217
218 /* Make sure the Thumb State bit is set. */
219 destination_address |= 0x1;
220
221 /* Branch execution */
222 __asm("BX %0" :: "r" (destination_address));
223}
224
225/* The following register is only present for
226 Cortex-M0+, -M23, -M3, -M33, -M4 and M7 CPUs */
227#if defined(CPU_CORE_CORTEX_M0PLUS) || defined(CPU_CORE_CORTEX_M23) || \
228 defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M33) || \
229 defined(CPU_CORE_CORTEX_M4) || defined(CPU_CORE_CORTEX_M4F) || \
230 defined(CPU_CORE_CORTEX_M7)
231static inline uint32_t cpu_get_image_baseaddr(void)
232{
233 return SCB->VTOR;
234}
235#endif
236
246bool cpu_check_address(volatile const char *address);
247
248#ifdef __cplusplus
249}
250#endif
251
static uinttxtptr_t cpu_get_caller_pc(void)
Get the last instruction's address.
Definition cpu.h:140
static uint32_t cpu_get_image_baseaddr(void)
Returns the address of running application in flash.
Definition cpu.h:29
MAYBE_INLINE void irq_restore(unsigned state)
This function restores the IRQ disable bit in the status register to the value contained within passe...
MAYBE_INLINE unsigned irq_disable(void)
This function sets the IRQ disable bit in the status register.
volatile unsigned int sched_context_switch_request
Flag indicating whether a context switch is necessary after handling an interrupt.
THREAD_MAYBE_INLINE void thread_yield_higher(void)
Lets current thread yield in favor of a higher prioritized thread.
void cortexm_init_misc(void)
Initialize Cortex-M misc functions.
static void cortexm_sleep(int deep)
Put the CPU into (deep) sleep mode, using the WFI instruction.
Definition cpu.h:154
static void cortexm_isr_end(void)
Trigger a conditional context scheduler run / context switch.
Definition cpu.h:179
static void cpu_jump_to_image(uint32_t image_address)
Jumps to another image in flash.
Definition cpu.h:193
void cortexm_init(void)
Initialize Cortex-M specific core parts of the CPU.
void cortexm_init_isr_priorities(void)
Initialize Cortex-M interrupt priorities.
#define CORTEXM_SCB_CPACR_FPU_ACCESS_FULL
Pattern to write into the co-processor Access Control Register to allow full FPU access.
Definition cpu.h:64
static void cortexm_sleep_until_event(void)
Put the CPU into the 'wait for event' sleep mode.
Definition cpu.h:144
bool cpu_check_address(volatile const char *address)
Checks is memory address valid or not.
static void cortexm_init_fpu(void)
Initialize Cortex-M FPU.
Definition cpu.h:91
IRQ driver interface.
Scheduler API definition.