cpu_conf_cc26xx_cc13xx.h

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/*
 * SPDX-FileCopyrightText: 2016 Leon George
 * SPDX-FileCopyrightText: 2020 Locha Inc
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include "kernel_defines.h"
 
#include "cpu_conf_common.h"
 
#include "cc26xx_cc13xx.h"
 
#include "cc26xx_cc13xx_adi.h"
#include "cc26xx_cc13xx_ccfg.h"
#include "cc26xx_cc13xx_gpio.h"
#include "cc26xx_cc13xx_gpt.h"
#include "cc26xx_cc13xx_hard_api.h"
#include "cc26xx_cc13xx_i2c.h"
#include "cc26xx_cc13xx_ioc.h"
#include "cc26xx_cc13xx_rfc.h"
#include "cc26xx_cc13xx_uart.h"
#include "cc26xx_cc13xx_vims.h"
#include "cc26xx_cc13xx_wdt.h"
 
#ifdef __cplusplus
extern "C" {
#endif

#define CPU_DEFAULT_IRQ_PRIO            (1U)
#define CPU_IRQ_NUMOF                   IRQN_COUNT
#define CPU_FLASH_BASE                  FLASH_BASE

#ifndef CONFIG_CC26XX_CC13XX_UPDATE_CCFG
#define CONFIG_CC26XX_CC13XX_UPDATE_CCFG            0
#endif

#ifndef CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH
#define CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH          0
#endif

#ifndef CONFIG_CC26XX_CC13XX_GPRAM
#define CONFIG_CC26XX_CC13XX_GPRAM                  0
#endif

#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_LEVEL_ACTIVE_HIGH)
#define CONFIG_CC26XX_CC13XX_BL_LEVEL               0x1
#elif IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_LEVEL_ACTIVE_LOW)
#define CONFIG_CC26XX_CC13XX_BL_LEVEL               0x0
#endif
 
#ifndef CONFIG_CC26XX_CC13XX_BL_LEVEL
#define CONFIG_CC26XX_CC13XX_BL_LEVEL               0x1
#endif

#ifndef CONFIG_CC26XX_CC13XX_BL_PIN
#define CONFIG_CC26XX_CC13XX_BL_PIN                 0xFF
#endif
 
/* high VDDR is available only on CC13xx CPUs */
#if IS_ACTIVE(CONFIG_CPU_FAM_CC13XX)
 
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH)
#define SET_MODE_CONF_1_ALT_DCDC_VMIN               0xC  
#define SET_MODE_CONF_VDDR_EXT_LOAD                 0x1  
#endif
 
#endif /* IS_ACTIVE(CONFIG_CPU_FAM_CC13XX) */
 
#if !IS_ACTIVE(CONFIG_CC26XX_CC13XX_GPRAM)
#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM            0x1  
#endif
 
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_ROM_BOOTLOADER)
#define SET_BL_CONFIG_BOOTLOADER_ENABLE             0xC5 
#define SET_BL_CONFIG_BL_ENABLE                     0xC5 
 
#if defined(CONFIG_CC26XX_CC13XX_BL_LEVEL)
#define SET_BL_CONFIG_BL_LEVEL                      CONFIG_CC26XX_CC13XX_BL_LEVEL
#endif
 
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_PIN_EN)
#define SET_BL_CONFIG_BL_PIN_NUMBER                 CONFIG_CC26XX_CC13XX_BL_PIN
#endif
 
#endif /* IS_USED(CONFIG_CC26XX_CC13XX_ROM_BOOTLOADER) */
 
/* when GPRAM is not disabled, use it as a backup RAM */
#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_DIS_GPRAM)
#define NUM_HEAPS (1)
#else
#define NUM_HEAPS (2)
#endif

#ifndef SET_EXT_LF_CLK_DIO
#define SET_EXT_LF_CLK_DIO                          0x01
#endif

#ifndef SET_EXT_LF_CLK_RTC_INCREMENT
#define SET_EXT_LF_CLK_RTC_INCREMENT                0x800000
#endif
 
#if defined(CPU_VARIANT_X2) || defined(DOXYGEN)
#ifndef SET_MODE_CONF_1_TCXO_TYPE
#define SET_MODE_CONF_1_TCXO_TYPE                   0x01
#endif

#ifndef SET_MODE_CONF_1_TCXO_MAX_START
#define SET_MODE_CONF_1_TCXO_MAX_START              0x7F
#endif
 
#endif /* defined(CPU_VARIANT_X2) || defined(DOXYGEN) */

#ifndef SET_MODE_CONF_1_ALT_DCDC_VMIN
#define SET_MODE_CONF_1_ALT_DCDC_VMIN               0x8
#endif

#ifndef SET_MODE_CONF_1_ALT_DCDC_DITHER_EN
#define SET_MODE_CONF_1_ALT_DCDC_DITHER_EN          0x0
#endif

#ifndef SET_MODE_CONF_1_ALT_DCDC_IPEAK
#define SET_MODE_CONF_1_ALT_DCDC_IPEAK              0x0
#endif

#ifndef SET_MODE_CONF_1_DELTA_IBIAS_INIT
#define SET_MODE_CONF_1_DELTA_IBIAS_INIT            0x0
#endif

#ifndef SET_MODE_CONF_1_DELTA_IBIAS_OFFSET
#define SET_MODE_CONF_1_DELTA_IBIAS_OFFSET          0x0
#endif

#ifndef SET_MODE_CONF_1_XOSC_MAX_START
#define SET_MODE_CONF_1_XOSC_MAX_START              0x10
#endif

#ifndef SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG
#define SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG         0x0058
#endif

#ifndef SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS
#define SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS    \
    (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_m >> \
     CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_s)
#endif

#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_TCXO
#define SET_SIZE_AND_DIS_FLAGS_DIS_TCXO             0x1
#endif

#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM
#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM            0x0
#endif

#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING
#define SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0
#endif

#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR
#define SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR         0x1
#endif

#ifndef SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA
#define SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA         0xF
#endif

#ifndef SET_MODE_CONF_DCDC_RECHARGE
#define SET_MODE_CONF_DCDC_RECHARGE                 0x0
#endif

#ifndef SET_MODE_CONF_DCDC_ACTIVE
#define SET_MODE_CONF_DCDC_ACTIVE                   0x0
#endif

#ifndef SET_MODE_CONF_VDDR_EXT_LOAD
#define SET_MODE_CONF_VDDR_EXT_LOAD                 0x0
#endif

#ifndef SET_MODE_CONF_VDDS_BOD_LEVEL
#define SET_MODE_CONF_VDDS_BOD_LEVEL                0x1
#endif

#ifndef SET_MODE_CONF_SCLK_LF_OPTION
#define SET_MODE_CONF_SCLK_LF_OPTION                0x2
#endif

#ifndef SET_MODE_CONF_VDDR_TRIM_SLEEP_TC
#define SET_MODE_CONF_VDDR_TRIM_SLEEP_TC            0x1
#endif

#ifndef SET_MODE_CONF_RTC_COMP
#define SET_MODE_CONF_RTC_COMP                      0x1
#endif

#ifndef SET_MODE_CONF_XOSC_FREQ
#define SET_MODE_CONF_XOSC_FREQ                     0x2
#endif

#ifndef SET_MODE_CONF_XOSC_CAP_MOD
#define SET_MODE_CONF_XOSC_CAP_MOD                  0x1
#endif

#ifndef SET_MODE_CONF_HF_COMP
#define SET_MODE_CONF_HF_COMP                       0x1
#endif

#ifndef SET_MODE_CONF_XOSC_CAPARRAY_DELTA
#define SET_MODE_CONF_XOSC_CAPARRAY_DELTA           0xFF
#endif

#ifndef SET_MODE_CONF_VDDR_CAP
#define SET_MODE_CONF_VDDR_CAP                      0x3A
#endif

#ifndef SET_BL_CONFIG_BOOTLOADER_ENABLE
#define SET_BL_CONFIG_BOOTLOADER_ENABLE             0x00
#endif

#ifndef SET_BL_CONFIG_BL_LEVEL
#define SET_BL_CONFIG_BL_LEVEL                      0x1
#endif

#ifndef SET_BL_CONFIG_BL_PIN_NUMBER
#define SET_BL_CONFIG_BL_PIN_NUMBER                 0xFF
#endif

#ifndef SET_BL_CONFIG_BL_ENABLE
#define SET_BL_CONFIG_BL_ENABLE                     0xFF
#endif

#ifndef SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE
#define SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE           0xC5
#endif

#ifndef SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE
#define SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE       0xC5
#endif

#ifndef SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE
#define SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE          0x00
#endif
 
#ifdef __cplusplus
}
#endif