cpu_conf.h

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/*
 * SPDX-FileCopyrightText: 2015-2017 Freie Universität Berlin
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include "cpu_conf_common.h"
 
#include "em_device.h"
 
#ifdef __cplusplus
extern "C" {
#endif

#define CPU_DEFAULT_IRQ_PRIO            (1U)
#define CPU_IRQ_NUMOF                   (EXT_IRQ_COUNT + 1)
#define CPU_FLASH_BASE                  (FLASH_BASE)

#define FLASHPAGE_SIZE                  (FLASH_PAGE_SIZE)
#define FLASHPAGE_NUMOF                 (FLASH_SIZE / FLASH_PAGE_SIZE)
/* The minimum block size which can be written is 4B. However, the erase
 * block is always FLASHPAGE_SIZE.
 */
#define FLASHPAGE_WRITE_BLOCK_SIZE      (4U)
/* Writing should be always 4 bytes aligned */
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)

#ifdef BITBAND_RAM_BASE
#define CPU_HAS_BITBAND 1
#endif
 
#ifdef __cplusplus
}
#endif