irq_arch.h

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/*
 * SPDX-FileCopyrightText: 2018 Gunar Schorcht
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include "irq_arch_common.h"
 
#ifdef __cplusplus
extern "C" {
#endif

 
/* On Xtensa-based ESP32x SoCs, interrupt 0 is reserved for the WiFi interface
 * and interrupt 1 is available. However, since interrupt 0 is not available on
 * RISC-V-based ESP32x SoCs, interrupt 1 is used for the WiFi interface instead.
 * Therefore, we use interrupt 1 for the RMT peripheral on Xtensa-based ESP32x
 * SoCs, but we use interrupt 11 for the RMT peripheral on RISC-V-based ESP32x
 * SoCs. Interrupt 11 is reserved for profiling on Xtensa-based ESP32x SoCs. */
#if defined(__XTENSA__)
#  define CPU_INUM_RMT           1  
#else
#  define CPU_INUM_RMT          11  
#endif
#define CPU_INUM_GPIO            2  
#define CPU_INUM_BLE             5  
#define CPU_INUM_BT_MAC          8  
#define CPU_INUM_RTT             9  
#define CPU_INUM_SERIAL_JTAG    10  
#define CPU_INUM_I2C            12  
#define CPU_INUM_UART           13  
#define CPU_INUM_CAN            17  
#define CPU_INUM_ETH            18  
#define CPU_INUM_USB            18  
#define CPU_INUM_LCDCAM         19  
#define CPU_INUM_FRC2           20  
#define CPU_INUM_SYSTIMER       20  
#define CPU_INUM_SDMMC          21  
#define CPU_INUM_TIMER          22  
#define CPU_INUM_WDT            23  
#define CPU_INUM_ZMAC           27  
#define CPU_INUM_SOFTWARE       29  

void esp_irq_init(void);
 
#ifdef __cplusplus
}
#endif