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board.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Eistec AB
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "cpu.h"
19#include "board_common.h"
20#include "periph_conf.h"
21
22#ifdef __cplusplus
23extern "C"
24{
25#endif
26
31#define LED0_PIN GPIO_PIN(PORT_B, 0)
32#define LED0_MASK (1 << 0)
33#define LED0_ON (GPIOB->PCOR = LED0_MASK)
34#define LED0_OFF (GPIOB->PSOR = LED0_MASK)
35#define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK)
36#define LED1_PIN GPIO_PIN(PORT_C, 1)
37#define LED1_MASK (1 << 1)
38#define LED1_ON (GPIOC->PCOR = LED1_MASK)
39#define LED1_OFF (GPIOC->PSOR = LED1_MASK)
40#define LED1_TOGGLE (GPIOC->PTOR = LED1_MASK)
41#define LED2_PIN GPIO_PIN(PORT_A, 19)
42#define LED2_MASK (1 << 19)
43#define LED2_ON (GPIOA->PCOR = LED2_MASK)
44#define LED2_OFF (GPIOA->PSOR = LED2_MASK)
45#define LED2_TOGGLE (GPIOA->PTOR = LED2_MASK)
46#define LED3_PIN GPIO_PIN(PORT_A, 18)
47#define LED3_MASK (1 << 18)
48#define LED3_ON (GPIOA->PCOR = LED3_MASK)
49#define LED3_OFF (GPIOA->PSOR = LED3_MASK)
50#define LED3_TOGGLE (GPIOA->PTOR = LED3_MASK)
52
57/* SW3, SW4 will short these pins to ground when pushed but there are no
58 * external pull resistors, use internal pull-ups on the pins */
59/* BTN0 is mapped to SW3 */
60#define BTN0_PIN GPIO_PIN(PORT_C, 4)
61#define BTN0_MODE GPIO_IN_PU
62/* BTN1 is mapped to SW4 */
63#define BTN1_PIN GPIO_PIN(PORT_C, 5)
64#define BTN1_MODE GPIO_IN_PU
66
71#if IS_ACTIVE(KINETIS_XTIMER_SOURCE_PIT)
72/* PIT xtimer configuration */
73#define XTIMER_DEV (TIMER_PIT_DEV(0))
74#define XTIMER_CHAN (0)
75/* Default xtimer settings should work on the PIT */
76#else
77/* LPTMR xtimer configuration */
78#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
79#define XTIMER_CHAN (0)
80/* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
81#define XTIMER_WIDTH (16)
82#define XTIMER_BACKOFF (5)
83#define XTIMER_ISR_BACKOFF (5)
84#define XTIMER_HZ (32768ul)
85#endif
87
92#define CONFIG_ZTIMER_USEC_TYPE ZTIMER_TYPE_PERIPH_TIMER
93#define CONFIG_ZTIMER_USEC_DEV (TIMER_PIT_DEV(0))
95
100#define FRDM_NOR_SPI_DEV SPI_DEV(0)
101#define FRDM_NOR_SPI_CLK SPI_CLK_5MHZ
102#define FRDM_NOR_SPI_CS SPI_HWCS(0)
104
109#define FXOS8700_PARAM_I2C I2C_DEV(0)
110#define FXOS8700_PARAM_ADDR 0x1F
112
113#ifdef __cplusplus
114}
115#endif
116