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lis2dh12_registers.h
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1/*
2 * Copyright (C) 2021 ML!PA Consulting GmbH
3 *
4 */
5
6#pragma once
7
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
26
30enum {
33};
34
38enum {
41};
42
46enum {
55};
56
60enum {
69};
70
74enum {
83};
84
88enum {
89 /* for interrupt 1 (CTRL_REG3) */
96
97 /* for interrupt 2 (CTRL_REG6) */
104
108};
109
113enum {
117};
118
122#define LIS2DH12_INT_SRC_1(ret) (((uint32_t)(ret) >> 0) & 0x7F)
123
127#define LIS2DH12_INT_SRC_2(ret) (((uint32_t)(ret) >> 8) & 0x7F)
128
132#define LIS2DH12_INT_SRC_CLICK(ret) (((uint32_t)(ret) >> 16) & 0x7F)
133
137typedef union {
138 struct {
139 uint8_t X_AXIS:1;
140 uint8_t Y_AXIS:1;
141 uint8_t Z_AXIS:1;
142 uint8_t Sign:1;
143 uint8_t SClick:1;
144 uint8_t DClick:1;
145 uint8_t IA:1;
147 uint8_t _RESERVED:1;
148 } bit;
149 uint8_t reg;
151
155typedef union {
156 struct {
157 uint8_t FSS:5;
158 uint8_t EMPTY:1;
159 uint8_t OVRN_FIFO:1;
160 uint8_t WTM:1;
161 } bit;
162 uint8_t reg;
164
165
174typedef union {
175 struct {
177 uint8_t SDO_PU_DISC:1;
178 } bit;
179 uint8_t reg;
181
185typedef union {
186 struct {
187 uint8_t _RESERVED:6;
188 uint8_t TEMP_EN:2;
189 } bit;
190 uint8_t reg;
192
196typedef union {
197 struct {
198 uint8_t Xen:1;
199 uint8_t Yen:1;
200 uint8_t Zen:1;
201 uint8_t LPen:1;
202 uint8_t ODR:4;
203 } bit;
204 uint8_t reg;
206
207#define LIS2DH12_CTRL_REG2_HP_IA1 (1 << 0)
208#define LIS2DH12_CTRL_REG2_HP_IA2 (1 << 1)
209#define LIS2DH12_CTRL_REG2_HPCLICK (1 << 2)
210#define LIS2DH12_CTRL_REG2_FDS (1 << 3)
211
212#define LIS2DH12_CLICK_THS_LIR (0x80)
213
217typedef union {
218 struct {
219 uint8_t HP_IA1:1;
220 uint8_t HP_IA2:1;
221 uint8_t HPCLICK:1;
222 uint8_t FDS:1;
223 uint8_t HPCF:2;
224 uint8_t HPM:2;
225 } bit;
226 uint8_t reg;
228
232typedef union {
233 struct {
234 uint8_t _RESERVED0:1;
235 uint8_t I1_OVERRUN:1;
236 uint8_t I1_WTM:1;
237 uint8_t _RESERVED3:1;
238 uint8_t I1_ZYXDA:1;
239 uint8_t I1_IA2:1;
240 uint8_t I1_IA1:1;
241 uint8_t I1_CLICK:1;
242 } bit;
243 uint8_t reg;
245
249typedef union {
250 struct {
251 uint8_t SPIM:1;
252 uint8_t ST:2;
253 uint8_t HR:1;
254 uint8_t FS:2;
255 uint8_t BLE:1;
256 uint8_t BDU:1;
257 } bit;
258 uint8_t reg;
260
264typedef union {
265 struct {
266 uint8_t D4D_INT2:1;
267 uint8_t LIR_INT2:1;
268 uint8_t D4D_INT1:1;
269 uint8_t LIR_INT1:1;
270 uint8_t _RESERVED:2;
271 uint8_t FIFO_EN:1;
272 uint8_t BOOT:1;
273 } bit;
274 uint8_t reg;
276
280typedef union {
281 struct {
282 uint8_t _RESERVED0:1;
283 uint8_t INT_POLARITY:1;
284 uint8_t _RESERVED2:1;
285 uint8_t I2_ACT:1;
286 uint8_t I2_BOOT:1;
287 uint8_t I2_IA2:1;
288 uint8_t I2_IA1:1;
289 uint8_t I2_CLICK:1;
290 } bit;
291 uint8_t reg;
293
297typedef union {
298 uint8_t reg;
300
304typedef union {
305 struct {
306 uint8_t FTH:5;
307 uint8_t TR:1;
308 uint8_t FM:2;
309 } bit;
310 uint8_t reg;
312
316typedef union {
317 struct {
318 uint8_t XLIE:1;
319 uint8_t XHIE:1;
320 uint8_t YLIE:1;
321 uint8_t YHIE:1;
322 uint8_t ZLIE:1;
323 uint8_t ZHIE:1;
324 uint8_t D6D:1;
325 uint8_t AOI:1;
326 } bit;
327 uint8_t reg;
329
333typedef union {
334 struct {
335 uint8_t THS:7;
338 uint8_t _RESERVED:1;
339 } bit;
340 uint8_t reg;
342
346typedef union {
347 struct {
348 uint8_t D:7;
349 uint8_t _RESERVED:1;
350 } bit;
351 uint8_t reg;
353
357typedef union {
358 struct {
359 uint8_t XLIE:1;
360 uint8_t XHIE:1;
361 uint8_t YLIE:1;
362 uint8_t YHIE:1;
363 uint8_t ZLIE:1;
364 uint8_t ZHIE:1;
365 uint8_t D6D:1;
366 uint8_t AOI:1;
367 } bit;
368 uint8_t reg;
370
374typedef union {
375 struct {
376 uint8_t THS:7;
377 uint8_t _RESERVED:1;
378 } bit;
379 uint8_t reg;
381
385typedef union {
386 struct {
387 uint8_t D:7;
388 uint8_t _RESERVED:1;
389 } bit;
390 uint8_t reg;
392
396typedef union {
397 struct {
398 uint8_t XS:1;
399 uint8_t XD:1;
400 uint8_t YS:1;
401 uint8_t YD:1;
402 uint8_t ZS:1;
403 uint8_t ZD:1;
404 uint8_t _RESERVED:2;
405 } bit;
406 uint8_t reg;
408
412typedef union {
413 struct {
414 uint8_t THS:7;
415 uint8_t LIR_CLICK:1;
418 } bit;
419 uint8_t reg;
421
425typedef union {
426 struct {
427 uint8_t TLI:7;
428 uint8_t _RESERVED:1;
429 } bit;
430 uint8_t reg;
432
436typedef union {
437 uint8_t reg;
439
443typedef union {
444 uint8_t reg;
446
450typedef union {
451 struct {
452 uint8_t ACTH:7;
454 uint8_t _RESERVED:1;
455 } bit;
456 uint8_t reg;
458
462typedef union {
463 uint8_t reg;
465
466
467#ifdef __cplusplus
468}
469#endif
470
@ LIS2DH12_TEMP_CFG_REG_DISABLE
Temperature sensor disable.
@ LIS2DH12_TEMP_CFG_REG_ENABLE
Temperature sensor enable.
@ LIS2DH12_INT_CFG_ZHIE
enable Z high event
@ LIS2DH12_INT_CFG_YHIE
enable Y high event
@ LIS2DH12_INT_CFG_XLIE
enable X low event
@ LIS2DH12_INT_CFG_6D
enable 6-direction detection
@ LIS2DH12_INT_CFG_XHIE
enable X high event
@ LIS2DH12_INT_CFG_ZLIE
enable Z low event
@ LIS2DH12_INT_CFG_YLIE
enable Y low event
@ LIS2DH12_INT_CFG_AOI
and/or combination interrupt events
@ LIS2DH12_STATUS_REG_ZYXDA
On X-, Y-, Z-axis new data available.
@ LIS2DH12_STATUS_REG_YOR
Y-axis data overrun.
@ LIS2DH12_STATUS_REG_XOR
X-axis data overrun.
@ LIS2DH12_STATUS_REG_ZOR
Y-axis data overrun.
@ LIS2DH12_STATUS_REG_YDA
Y-axis new data available.
@ LIS2DH12_STATUS_REG_XDA
X-axis new data available.
@ LIS2DH12_STATUS_REG_ZDA
Z-axis new data available.
@ LIS2DH12_STATUS_REG_ZYXOR
On X-, Y-, Z-axis data overrun.
@ LIS2DH12_STATUS_REG_AUX_TOR
Temperature data overrun.
@ LIS2DH12_STATUS_REG_AUX_TDA
Temperature new data available.
@ LIS2DH12_INT_TYPE_I1_WTM
FIFO watermark interrupt on INT1.
@ LIS2DH12_INT_TYPE_I1_ZYXDA
ZYXDA interrupt on INT1.
@ LIS2DH12_INT_TYPE_I2_IA2
IA2 on INT2.
@ LIS2DH12_INT_TYPE_I2_ACT
enable activity interrupt on INT2
@ LIS2DH12_INT_TYPE_I2_CLICK
click interrupt on INT2
@ LIS2DH12_INT_TYPE_CLICK
click interrupt
@ LIS2DH12_INT_TYPE_IA2
Event 2.
@ LIS2DH12_INT_TYPE_I2_IA1
IA1 on INT2.
@ LIS2DH12_INT_TYPE_I1_IA2
IA2 interrupt on INT1.
@ LIS2DH12_INT_TYPE_IA1
Event 1.
@ LIS2DH12_INT_TYPE_I2_BOOT
enable boot on INT2
@ LIS2DH12_INT_TYPE_I1_OVERRUN
FIFO overrun interrupt on INT1.
@ LIS2DH12_INT_TYPE_I1_IA1
IA1 interrupt on INT1.
@ LIS2DH12_INT_TYPE_INT_POLARITY
INT1 and INT2 pin polarity.
@ LIS2DH12_INT_TYPE_I1_CLICK
click interrupt on INT1
@ LIS2DH12_EVENT_2
second event slot
@ LIS2DH12_EVENT_1
first event slot
@ LIS2DH12_EVENT_CLICK
click event
@ LIS2DH12_INT_SRC_XL
X low event.
@ LIS2DH12_INT_SRC_XH
X high event.
@ LIS2DH12_INT_SRC_ZL
Z low event.
@ LIS2DH12_INT_SRC_ZH
Z high event.
@ LIS2DH12_INT_SRC_YL
Y low event.
@ LIS2DH12_INT_SRC_IA
Interrupt 1 active, at least one interrupt \ has been generated.
@ LIS2DH12_INT_SRC_YH
Y high event.
ACT_DURATION definitions.
uint8_t reg
Sleep-to-wake and return-to-sleep duration, in ODR cycles.
ACT_THS definitions.
uint8_t ACTH
Sets the threshold sleep-to-wake or return-to-sleep LSB according to LIS2DH12_SCALE.
uint8_t _RESERVED
reserved bit
uint8_t reg
Type used for register access.
CLICK_CFG definitions.
uint8_t _RESERVED
Reserved bits.
uint8_t XD
Interrupt double-click enable on X-axis.
uint8_t ZS
Interrupt single-click enable on Z-axis.
uint8_t reg
Type used for register access.
uint8_t YD
Interrupt double-click enable on Y-axis.
uint8_t YS
Interrupt single-click enable on Y-axis.
uint8_t ZD
Interrupt double-click enable on Z-axis.
uint8_t XS
Interrupt single-click enable on X-axis.
CLICK_SRC definitions.
uint8_t SClick
Single click detected.
uint8_t _RESERVED
Reserved bit.
uint8_t X_AXIS
X click detected.
uint8_t Z_AXIS
Z click detected.
uint8_t Y_AXIS
Y click detected.
uint8_t DClick
Double click detected.
uint8_t reg
Type used for register access.
uint8_t IA
Interrupt active, at least one interrupt \ has been generated.
uint8_t Sign
Click sign, "0" positive, "1" negative.
CLICK_THS definitions.
uint8_t reg
Type used for register access.
uint8_t LIR_CLICK
Enables latency on interrupt kept high, \ "0" for duration of latency window, \ "1" kept high until C...
uint8_t THS
Sets the click threshold, LSB according to LIS2DH12_SCALE.
CTRL_REG_0 definitions.
uint8_t CTRL0_DEFAULT_VALUE
Always set this to CTRL_REG0_DEFAULT.
uint8_t reg
Type used for register access.
uint8_t SDO_PU_DISC
disconnect pull-up on SDO/SA0
CTRL_REG1 definitions.
uint8_t Xen
X axis enable.
uint8_t reg
Type used for register access.
uint8_t ODR
Set Data rate.
uint8_t Zen
Z axis enable.
uint8_t Yen
Y axis enable.
uint8_t LPen
Enable Low Power mode.
CTRL_REG2 definitions.
uint8_t HPCLICK
High pass filter enable for CLICK function.
uint8_t HP_IA2
High pass filter enable for AOI on interrupt 2.
uint8_t HPCF
High pass filter cutoff frequency.
uint8_t HPM
High pass filter mode selection.
uint8_t reg
Type used for register access.
uint8_t HP_IA1
High pass filter enable for AOI on interrupt 1.
uint8_t FDS
Enables filter output data.
CTRL_REG3 definitions.
uint8_t I1_IA2
Enable IA2 interrupt on INT1.
uint8_t I1_OVERRUN
Enable FIFO overrun interrupt on INT1.
uint8_t _RESERVED3
Should always be "0".
uint8_t I1_CLICK
Enable CLICK interrupt on INT1.
uint8_t _RESERVED0
Reserved bit.
uint8_t I1_WTM
Enable FIFO watermark interrupt on INT1.
uint8_t I1_IA1
Enable IA1 interrupt on INT1.
uint8_t reg
Type used for register access.
uint8_t I1_ZYXDA
Enable ZYXDA interrupt on INT1.
CTRL_REG4 definitions.
uint8_t ST
Self-test enable.
uint8_t BDU
Block data update.
uint8_t BLE
Big/Little endian data selection.
uint8_t FS
Full-scale selection.
uint8_t reg
Type used for register access.
uint8_t SPIM
SPI serial interface mode selection (SIM)
uint8_t HR
Operating mode.
CTRL_REG5 definitions.
uint8_t D4D_INT2
4D detection enabled on INT2
uint8_t reg
Type used for register access.
uint8_t LIR_INT2
Latch interrupt request for INT2.
uint8_t D4D_INT1
4D detection enabled on INT1
uint8_t FIFO_EN
FIFO enable.
uint8_t _RESERVED
Reserved bits.
uint8_t LIR_INT1
Latch interrupt request for INT2.
uint8_t BOOT
Clears the data content.
CTRL_REG6 definitions.
uint8_t I2_IA1
Enable IA1 on INT2.
uint8_t I2_ACT
Enable activity interrupt on INT2.
uint8_t INT_POLARITY
Set pin polarity for INT1 and INT2.
uint8_t _RESERVED2
Reserved bit.
uint8_t _RESERVED0
Reserved bit.
uint8_t I2_IA2
Enable IA2 on INT2.
uint8_t reg
Type used for register access.
uint8_t I2_BOOT
Enable boot on INT2.
uint8_t I2_CLICK
Enable CLICK interrupt on INT2.
FIFO_CTRL_REG definitions.
uint8_t FTH
Set the watermark level for FIFO.
uint8_t TR
Triggering selection, FIFO event triggers INT1 or INT2.
uint8_t reg
Type used for register access.
uint8_t FM
FIFO mode selection.
FIFO_SRC_REG definitions.
uint8_t reg
Type used for register access.
uint8_t EMPTY
FIFO is empty.
uint8_t FSS
Number of unread samples in FIFO.
uint8_t WTM
FIFO content watermark level.
uint8_t OVRN_FIFO
Overrun in FIFO occurred.
INT1_CFG definitions.
uint8_t YLIE
Enable interrupt on Y low event.
uint8_t ZLIE
Enable interrupt on Z low event.
uint8_t AOI
AND/OR combination of interrupt events.
uint8_t ZHIE
Enable interrupt on Z high event.
uint8_t D6D
6 direction detection function enable
uint8_t reg
Type used for register access.
uint8_t YHIE
Enable interrupt on Y high event.
uint8_t XHIE
Enable interrupt on X high event.
uint8_t XLIE
Enable interrupt on X low event.
INT1_DURATION definitions.
uint8_t _RESERVED
need to be zero
uint8_t reg
Type used for register access.
uint8_t D
Sets the minimum duration of INT1, in ODR cycles.
INT1_THS definitions.
uint8_t reg
Type used for register access.
uint8_t THS
Sets threshold level, the LSB changes according to LIS2DH12_SCALE (@2G LSB=16mg; @4G LSB=32mg; @8G LS...
uint8_t _RESERVED
needs to be zero
INT2_CFG definitions.
uint8_t XLIE
Enable interrupt on X low event.
uint8_t reg
Type used for register access.
uint8_t YHIE
Enable interrupt on Y high event.
uint8_t YLIE
Enable interrupt on Y low event.
uint8_t AOI
AND/OR combination of interrupt events.
uint8_t ZLIE
Enable interrupt on Z low event.
uint8_t D6D
6 direction detection function enable
uint8_t XHIE
Enable interrupt on X high event.
uint8_t ZHIE
Enable interrupt on Z high event.
INT2_DURATION definitions.
uint8_t D
Sets the minimum duration of INT2, in ODR cycles.
uint8_t _RESERVED
need to be zero
uint8_t reg
Type used for register access.
INT2_THS definitions.
uint8_t reg
Type used for register access.
uint8_t _RESERVED
needs to be zero
uint8_t THS
Sets threshold level, LSB according to LIS2DH12_SCALE.
REFERENCE definitions.
uint8_t reg
Set reference value.
TEMP_CFG_REG definitions.
uint8_t _RESERVED
Should always be zero.
uint8_t TEMP_EN
"00" disables Temperature sensor, "11" enables
uint8_t reg
Type used for register access.
TIME_LATENCY definitions.
uint8_t reg
Sets time latency, in ODR cycles.
TIME_LIMIT definitions.
uint8_t reg
Type used for register access.
uint8_t _RESERVED
reserved bit
uint8_t TLI
Click time limit, in ODR cycles.
TIME_WINDOW definitions.
uint8_t reg
Sets time window, in ODR cycles.