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periph_conf.h
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1/*
2 * Copyright (C) 2016 Freie Universität Berlin
3 * 2016-2018 Inria
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
10#pragma once
11
25
26#include "periph_cpu.h"
27#include "periph_conf_common.h"
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
37static const uart_conf_t uart_config[] = {
38 {
39 .dev = &SERCOM5->USART,
40 .rx_pin = GPIO_PIN(PB,23), /* ARDUINO_PIN_13, RX Pin */
41 .tx_pin = GPIO_PIN(PB,22), /* ARDUINO_PIN_14, TX Pin */
42#ifdef MODULE_PERIPH_UART_HW_FC
43 .rts_pin = GPIO_UNDEF,
44 .cts_pin = GPIO_UNDEF,
45#endif
46 .mux = GPIO_MUX_D,
47 .rx_pad = UART_PAD_RX_3,
48 .tx_pad = UART_PAD_TX_2,
49 .flags = UART_FLAG_NONE,
50 .gclk_src = SAM0_GCLK_MAIN,
51 },
52 { /* LoRa module */
53 .dev = &SERCOM4->USART,
54 .rx_pin = GPIO_PIN(PA,15),
55 .tx_pin = GPIO_PIN(PA,12),
56#ifdef MODULE_PERIPH_UART_HW_FC
57 .rts_pin = GPIO_UNDEF,
58 .cts_pin = GPIO_UNDEF,
59#endif
60 .mux = GPIO_MUX_D,
61 .rx_pad = UART_PAD_RX_3,
62 .tx_pad = UART_PAD_TX_0,
63 .flags = UART_FLAG_NONE,
64 .gclk_src = SAM0_GCLK_MAIN,
65 },
66};
67
68/* interrupt function name mapping */
69#define UART_0_ISR isr_sercom5
70#define UART_1_ISR isr_sercom4
71
72#define UART_NUMOF ARRAY_SIZE(uart_config)
74
79static const spi_conf_t spi_config[] = {
80 {
81 .dev = &SERCOM1->SPI,
82 .miso_pin = GPIO_PIN(PA, 19), /* ARDUINO_PIN_8, SERCOM1-MISO */
83 .mosi_pin = GPIO_PIN(PA, 16), /* ARDUINO_PIN_10, SERCOM1-MOSI */
84 .clk_pin = GPIO_PIN(PA, 17), /* ARDUINO_PIN_9, SERCOM1-SCK */
85 .miso_mux = GPIO_MUX_C,
86 .mosi_mux = GPIO_MUX_C,
87 .clk_mux = GPIO_MUX_C,
88 .miso_pad = SPI_PAD_MISO_3,
89 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
90 .gclk_src = SAM0_GCLK_MAIN,
91 }
92};
93
94#define SPI_NUMOF ARRAY_SIZE(spi_config)
96
97#ifdef __cplusplus
98}
99#endif
100
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ UART_PAD_RX_3
select pad 3
@ SPI_PAD_MISO_3
use pad 3 for MISO line
@ UART_FLAG_NONE
No flags set.
@ PB
port B
@ PA
port A
@ UART_PAD_TX_0
select pad 0
@ UART_PAD_TX_2
select pad 2
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:73
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217