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cfg_i2c1_pb6_pb7.h
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1/*
2 * SPDX-FileCopyrightText: 2019 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
28static const i2c_conf_t i2c_config[] = {
29 {
30 .dev = I2C1,
31 .speed = I2C_SPEED_NORMAL,
32 .scl_pin = GPIO_PIN(PORT_B, 6),
33 .sda_pin = GPIO_PIN(PORT_B, 7),
34#if CPU_FAM_STM32L4
35 .scl_af = GPIO_AF4,
36 .sda_af = GPIO_AF4,
37#else /* CPU_FAM_STM32L0 */
38 .scl_af = GPIO_AF1,
39 .sda_af = GPIO_AF1,
40#endif
41 .bus = APB1,
42#if CPU_FAM_STM32L4
43 .rcc_mask = RCC_APB1ENR1_I2C1EN,
44 .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
45 .irqn = I2C1_ER_IRQn,
46#else /* CPU_FAM_STM32L0 */
47 .rcc_mask = RCC_APB1ENR_I2C1EN,
48 .irqn = I2C1_IRQn
49#endif
50 }
51};
52
53#if CPU_FAM_STM32L4
54#define I2C_0_ISR isr_i2c1_er
55#else /* CPU_FAM_STM32L0 */
56#define I2C_0_ISR isr_i2c1
57#endif
58
59#define I2C_NUMOF ARRAY_SIZE(i2c_config)
61#ifdef __cplusplus
62}
63#endif
64
@ PORT_B
port B
Definition periph_cpu.h:44
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:274
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
I2C configuration structure.
Definition periph_cpu.h:295