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cfg_i2c1_pb6_pb7.h
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1/*
2 * Copyright (C) 2019 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
20
21#include "periph_cpu.h"
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
31static const i2c_conf_t i2c_config[] = {
32 {
33 .dev = I2C1,
34 .speed = I2C_SPEED_NORMAL,
35 .scl_pin = GPIO_PIN(PORT_B, 6),
36 .sda_pin = GPIO_PIN(PORT_B, 7),
37#if CPU_FAM_STM32L4
38 .scl_af = GPIO_AF4,
39 .sda_af = GPIO_AF4,
40#else /* CPU_FAM_STM32L0 */
41 .scl_af = GPIO_AF1,
42 .sda_af = GPIO_AF1,
43#endif
44 .bus = APB1,
45#if CPU_FAM_STM32L4
46 .rcc_mask = RCC_APB1ENR1_I2C1EN,
47 .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
48 .irqn = I2C1_ER_IRQn,
49#else /* CPU_FAM_STM32L0 */
50 .rcc_mask = RCC_APB1ENR_I2C1EN,
51 .irqn = I2C1_IRQn
52#endif
53 }
54};
55
56#if CPU_FAM_STM32L4
57#define I2C_0_ISR isr_i2c1_er
58#else /* CPU_FAM_STM32L0 */
59#define I2C_0_ISR isr_i2c1
60#endif
61
62#define I2C_NUMOF ARRAY_SIZE(i2c_config)
64#ifdef __cplusplus
65}
66#endif
67
@ PORT_B
port B
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
I2C configuration structure.
Definition periph_cpu.h:298