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periph_conf_atmega_common.h
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1/*
2 * SPDX-FileCopyrightText: 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
3 * SPDX-FileCopyrightText: 2016 Laurent Navet <laurent.navet@gmail.com>
4 * SPDX-FileCopyrightText: 2016 RWTH Aachen, Josua Arndt
5 * SPDX-FileCopyrightText: 2016 INRIA, Francisco Acosta
6 * SPDX-FileCopyrightText: 2017 HAW Hamburg, Dimitri Nahm
7 * SPDX-FileCopyrightText: 2018 Matthew Blue <matthew.blue.neuro@gmail.com>
8 * SPDX-FileCopyrightText: 2019 Otto-von-Guericke-Universität Magdeburg
9 * SPDX-FileCopyrightText: 2023 Hugues Larrive
10 * SPDX-License-Identifier: LGPL-2.1-only
11 */
12
13#pragma once
14
33
34#include "periph_cpu.h"
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
44#ifndef CLOCK_CORECLOCK
45#define CLOCK_CORECLOCK (16000000UL)
46#endif /* CLOCK_CORECLOCK */
48
58
59#ifndef UART_NUMOF
60#if defined(CPU_ATMEGA128RFA1) || defined(CPU_ATMEGA256RFR2) || \
61 defined(CPU_ATMEGA1281) || defined(CPU_ATMEGA1284P) || defined(CPU_ATMEGA2560)
62 #define UART_NUMOF (2U)
63
64 /* UART0 is used for stdio */
65 #define UART_0 MEGA_UART0
66 #define UART_0_ISR USART0_RX_vect
67 #define UART_0_ISR_TX USART0_TX_vect
68
69 #define UART_1 MEGA_UART1
70 #define UART_1_ISR USART1_RX_vect
71 #define UART_1_ISR_TX USART1_TX_vect
72#elif defined(CPU_ATMEGA8)
73 #define UART_NUMOF (1U)
74
75 #define UART_0 MEGA_UART
76 #define UART_0_ISR USART_RXC_vect
77 #define UART_0_ISR_TX USART_TXC_vect
78#elif defined(CPU_ATMEGA328P)
79 #define UART_NUMOF (1U)
80
81 #define UART_0 MEGA_UART0
82 #define UART_0_ISR USART_RX_vect
83 #define UART_0_ISR_TX USART_TX_vect
84#elif defined(CPU_ATMEGA32U4)
85 #define UART_NUMOF (1U)
86
87 #define UART_0 MEGA_UART1
88 #define UART_0_ISR USART1_RX_vect
89 #define UART_0_ISR_TX USART1_TX_vect
90#else
91 #define UART_NUMOF (0U)
92#endif
93#endif /* UART_NUMOF */
95
136#ifndef SPI_NUMOF
137#define SPI_NUMOF (1U)
138#endif /* SPI_NUMOF */
140
145#ifndef I2C_NUMOF
146#define I2C_BUS_SPEED I2C_SPEED_FAST
147#define I2C_NUMOF (1U)
148#endif /* I2C_NUMOF */
150
161#ifndef ADC_NUMOF
162#if defined(CPU_ATMEGA128RFA1) || defined(CPU_ATMEGA256RFR2) || defined(CPU_ATMEGA328P) || \
163 defined(CPU_ATMEGA1281) || defined(CPU_ATMEGA1284P) || defined(CPU_ATMEGA32U4) || \
164 defined(CPU_ATMEGA8)
165 #define ADC_NUMOF (8U)
166#elif defined (CPU_ATMEGA2560)
167 #define ADC_NUMOF (16U)
168#else
169 #define ADC_NUMOF (0U)
170#endif
171#endif /* ADC_NUMOF */
173
187#ifndef PWM_NUMOF
188#if defined(CPU_ATMEGA8)
189 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 3), GPIO_UNDEF }
190#elif defined(CPU_ATMEGA328P)
191 #define PWM_PINS_CH0 { GPIO_PIN(PORT_D, 6), GPIO_PIN(PORT_D, 5) }
192 #define PWM_PINS_CH1 { GPIO_PIN(PORT_B, 3), GPIO_PIN(PORT_D, 3) }
193#elif defined(CPU_ATMEGA1281)
194 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 7), GPIO_PIN(PORT_G, 5) }
195 #define PWM_PINS_CH1 { GPIO_PIN(PORT_B, 4), GPIO_UNDEF }
196#elif defined(CPU_ATMEGA1284P)
197 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 3), GPIO_PIN(PORT_B, 4) }
198 #define PWM_PINS_CH1 { GPIO_PIN(PORT_D, 7), GPIO_PIN(PORT_D, 6) }
199#elif defined(CPU_ATMEGA2560)
200 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 7), GPIO_PIN(PORT_G, 5) }
201 #define PWM_PINS_CH1 { GPIO_PIN(PORT_B, 4), GPIO_PIN(PORT_H, 6) }
202#elif defined(CPU_ATMEGA32U4)
203 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 7), GPIO_PIN(PORT_D, 0) }
204#else
205 #define PWM_NUMOF (0U)
206#endif
207
208#if defined(CPU_ATMEGA32U4) || defined(CPU_ATMEGA328P) || \
209 defined(CPU_ATMEGA1281) || defined(CPU_ATMEGA1284P) || \
210 defined(CPU_ATMEGA2560) || defined(CPU_ATMEGA8)
211 static const pwm_conf_t pwm_conf[] = {
212#ifndef CPU_ATMEGA8
213 {
214 .dev = MINI_TIMER0,
215 .pin_ch = PWM_PINS_CH0,
216 .div = MINI_TIMER0_DIV,
217 },
218#ifndef CPU_ATMEGA32U4
219 {
220 .dev = MINI_TIMER2,
221 .pin_ch = PWM_PINS_CH1,
222 .div = MINI_TIMER2_DIV,
223 }
224#endif
225#else /* CPU_ATMEGA8 */
226 {
227 .dev = MINI_TIMER2,
228 .pin_ch = PWM_PINS_CH0,
229 .div = MINI_TIMER2_DIV,
230 },
231#endif
232 };
233
234 #define PWM_NUMOF ARRAY_SIZE(pwm_conf)
235#endif
236#endif /* PWM_NUMOF */
238
239#ifdef __cplusplus
240}
241#endif
242
PWM device configuration.