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periph_conf_atmega_common.h
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1/*
2 * Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
3 * 2016 Laurent Navet <laurent.navet@gmail.com>
4 * 2016 RWTH Aachen, Josua Arndt
5 * 2016 INRIA, Francisco Acosta
6 * 2017 HAW Hamburg, Dimitri Nahm
7 * 2018 Matthew Blue <matthew.blue.neuro@gmail.com>
8 * 2019 Otto-von-Guericke-Universität Magdeburg
9 * 2023 Hugues Larrive
10 *
11 * This file is subject to the terms and conditions of the GNU Lesser
12 * General Public License v2.1. See the file LICENSE in the top level
13 * directory for more details.
14 */
15
16#pragma once
17
36
37#include "periph_cpu.h"
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
47#ifndef CLOCK_CORECLOCK
48#define CLOCK_CORECLOCK (16000000UL)
49#endif /* CLOCK_CORECLOCK */
51
61
62#ifndef UART_NUMOF
63#if defined(CPU_ATMEGA128RFA1) || defined(CPU_ATMEGA256RFR2) || \
64 defined(CPU_ATMEGA1281) || defined(CPU_ATMEGA1284P) || defined(CPU_ATMEGA2560)
65 #define UART_NUMOF (2U)
66
67 /* UART0 is used for stdio */
68 #define UART_0 MEGA_UART0
69 #define UART_0_ISR USART0_RX_vect
70 #define UART_0_ISR_TX USART0_TX_vect
71
72 #define UART_1 MEGA_UART1
73 #define UART_1_ISR USART1_RX_vect
74 #define UART_1_ISR_TX USART1_TX_vect
75#elif defined(CPU_ATMEGA8)
76 #define UART_NUMOF (1U)
77
78 #define UART_0 MEGA_UART
79 #define UART_0_ISR USART_RXC_vect
80 #define UART_0_ISR_TX USART_TXC_vect
81#elif defined(CPU_ATMEGA328P)
82 #define UART_NUMOF (1U)
83
84 #define UART_0 MEGA_UART0
85 #define UART_0_ISR USART_RX_vect
86 #define UART_0_ISR_TX USART_TX_vect
87#elif defined(CPU_ATMEGA32U4)
88 #define UART_NUMOF (1U)
89
90 #define UART_0 MEGA_UART1
91 #define UART_0_ISR USART1_RX_vect
92 #define UART_0_ISR_TX USART1_TX_vect
93#else
94 #define UART_NUMOF (0U)
95#endif
96#endif /* UART_NUMOF */
98
139#ifndef SPI_NUMOF
140#define SPI_NUMOF (1U)
141#endif /* SPI_NUMOF */
143
148#ifndef I2C_NUMOF
149#define I2C_BUS_SPEED I2C_SPEED_FAST
150#define I2C_NUMOF (1U)
151#endif /* I2C_NUMOF */
153
164#ifndef ADC_NUMOF
165#if defined(CPU_ATMEGA128RFA1) || defined(CPU_ATMEGA256RFR2) || defined(CPU_ATMEGA328P) || \
166 defined(CPU_ATMEGA1281) || defined(CPU_ATMEGA1284P) || defined(CPU_ATMEGA32U4) || \
167 defined(CPU_ATMEGA8)
168 #define ADC_NUMOF (8U)
169#elif defined (CPU_ATMEGA2560)
170 #define ADC_NUMOF (16U)
171#else
172 #define ADC_NUMOF (0U)
173#endif
174#endif /* ADC_NUMOF */
176
190#ifndef PWM_NUMOF
191#if defined(CPU_ATMEGA8)
192 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 3), GPIO_UNDEF }
193#elif defined(CPU_ATMEGA328P)
194 #define PWM_PINS_CH0 { GPIO_PIN(PORT_D, 6), GPIO_PIN(PORT_D, 5) }
195 #define PWM_PINS_CH1 { GPIO_PIN(PORT_B, 3), GPIO_PIN(PORT_D, 3) }
196#elif defined(CPU_ATMEGA1281)
197 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 7), GPIO_PIN(PORT_G, 5) }
198 #define PWM_PINS_CH1 { GPIO_PIN(PORT_B, 4), GPIO_UNDEF }
199#elif defined(CPU_ATMEGA1284P)
200 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 3), GPIO_PIN(PORT_B, 4) }
201 #define PWM_PINS_CH1 { GPIO_PIN(PORT_D, 7), GPIO_PIN(PORT_D, 6) }
202#elif defined(CPU_ATMEGA2560)
203 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 7), GPIO_PIN(PORT_G, 5) }
204 #define PWM_PINS_CH1 { GPIO_PIN(PORT_B, 4), GPIO_PIN(PORT_H, 6) }
205#elif defined(CPU_ATMEGA32U4)
206 #define PWM_PINS_CH0 { GPIO_PIN(PORT_B, 7), GPIO_PIN(PORT_D, 0) }
207#else
208 #define PWM_NUMOF (0U)
209#endif
210
211#if defined(CPU_ATMEGA32U4) || defined(CPU_ATMEGA328P) || \
212 defined(CPU_ATMEGA1281) || defined(CPU_ATMEGA1284P) || \
213 defined(CPU_ATMEGA2560) || defined(CPU_ATMEGA8)
214 static const pwm_conf_t pwm_conf[] = {
215#ifndef CPU_ATMEGA8
216 {
217 .dev = MINI_TIMER0,
218 .pin_ch = PWM_PINS_CH0,
219 .div = MINI_TIMER0_DIV,
220 },
221#ifndef CPU_ATMEGA32U4
222 {
223 .dev = MINI_TIMER2,
224 .pin_ch = PWM_PINS_CH1,
225 .div = MINI_TIMER2_DIV,
226 }
227#endif
228#else /* CPU_ATMEGA8 */
229 {
230 .dev = MINI_TIMER2,
231 .pin_ch = PWM_PINS_CH0,
232 .div = MINI_TIMER2_DIV,
233 },
234#endif
235 };
236
237 #define PWM_NUMOF ARRAY_SIZE(pwm_conf)
238#endif
239#endif /* PWM_NUMOF */
241
242#ifdef __cplusplus
243}
244#endif
245
PWM device configuration.