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periph_cpu.h
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1/*
2 * Copyright (C) 2016 Freie Universität Berlin
3 * 2017 OTA keys S.A.
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
10#pragma once
11
22
23#include <limits.h>
24
25#include "cpu.h"
26#include "macros/units.h"
27
28#if defined(CPU_FAM_STM32F0)
30#elif defined(CPU_FAM_STM32F1)
32#elif defined(CPU_FAM_STM32F2)
34#elif defined(CPU_FAM_STM32F3)
36#elif defined(CPU_FAM_STM32F4)
38#elif defined(CPU_FAM_STM32F7)
40#elif defined(CPU_FAM_STM32G0)
42#elif defined(CPU_FAM_STM32C0)
44#elif defined(CPU_FAM_STM32G4)
46#elif defined(CPU_FAM_STM32L0)
48#elif defined(CPU_FAM_STM32L1)
50#elif defined(CPU_FAM_STM32L4)
52#elif defined(CPU_FAM_STM32L5)
54#elif defined(CPU_FAM_STM32U5)
56#elif defined(CPU_FAM_STM32WB)
58#elif defined(CPU_FAM_STM32WL)
60#endif
61
63#include "periph/cpu_common.h"
64#include "periph/cpu_dma.h"
65#include "periph/cpu_eth.h"
66#include "periph/cpu_fmc.h"
67#include "periph/cpu_gpio.h"
68#include "periph/cpu_gpio_ll.h"
69#include "periph/cpu_i2c.h"
70#include "periph/cpu_ltdc.h"
71#include "periph/cpu_pm.h"
72#include "periph/cpu_pwm.h"
73#include "periph/cpu_qdec.h"
74#include "periph/cpu_sdmmc.h"
75#include "periph/cpu_spi.h"
76#include "periph/cpu_timer.h"
77#include "periph/cpu_uart.h"
78#include "periph/cpu_usbdev.h"
79#include "periph/cpu_vbat.h"
80#include "periph/cpu_wdt.h"
81
82#ifdef MODULE_PERIPH_CAN
83#ifdef MODULE_FDCAN
84#include "fdcandev_stm32.h"
85#else
86#include "candev_stm32.h"
87#endif
88#endif
89
90#ifdef __cplusplus
91extern "C" {
92#endif
93
97typedef struct {
98 gpio_t pin;
99#if !defined(CPU_FAM_STM32F0) && !defined(CPU_FAM_STM32L0) && \
100 !defined(CPU_FAM_STM32L1) && !defined(CPU_FAM_STM32WL)
101 uint8_t dev;
102#endif
103 uint8_t chan;
104} adc_conf_t;
105
109typedef struct {
110 gpio_t pin;
111 uint8_t chan;
112} dac_conf_t;
113
118#define HAVE_PTP_CLOCK_READ 1
119#define HAVE_PTP_CLOCK_SET 1
120#define HAVE_PTP_TIMER_SET_ABSOLUTE 1
122
123#if !DOXYGEN /* hide implementation details */
128/* Detect the IP version based on the available register define */
129#if defined(USB_OTG_GCCFG_NOVBUSSENS)
130#define STM32_USB_OTG_CID_1x
131#elif defined(USB_OTG_GCCFG_VBDEN)
132#define STM32_USB_OTG_CID_2x
133#elif defined(USB)
134#define STM32_USB_FS_CID_1x
135#endif
136
141#if defined(USB_OTG_FS_MAX_IN_ENDPOINTS)
142#define STM32_USB_OTG_FS_NUM_EP (USB_OTG_FS_MAX_IN_ENDPOINTS)
143#elif defined(STM32_USB_OTG_CID_1x)
144#define STM32_USB_OTG_FS_NUM_EP (4)
145#elif defined(STM32_USB_OTG_CID_2x)
146#define STM32_USB_OTG_FS_NUM_EP (6)
147#endif
148
153#if defined(USB_OTG_HS_MAX_IN_ENDPOINTS)
154#define STM32_USB_OTG_HS_NUM_EP (USB_OTG_HS_MAX_IN_ENDPOINTS)
155#elif defined(STM32_USB_OTG_CID_1x)
156#define STM32_USB_OTG_HS_NUM_EP (6)
157#elif defined(STM32_USB_OTG_CID_2x)
158#define STM32_USB_OTG_HS_NUM_EP (9)
159#endif
160
171#if defined(MODULE_PERIPH_USBDEV_HS) && defined(STM32_USB_OTG_HS_NUM_EP)
172#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_HS_NUM_EP
173#elif defined(STM32_USB_OTG_FS_NUM_EP)
174#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_FS_NUM_EP
175#else
176#define USBDEV_NUM_ENDPOINTS 8
177#endif
178
179/* unify names across STM32 families */
180#ifdef SPI_CR1_CPHA_Msk
181# define STM32_SPI_CPHA_Msk SPI_CR1_CPHA_Msk
182#endif
183#ifdef SPI_CFG2_CPHA_Msk
184# define STM32_SPI_CPHA_Msk SPI_CFG2_CPHA_Msk
185#endif
186#ifdef SPI_CR1_CPOL_Msk
187# define STM32_SPI_CPOL_Msk SPI_CR1_CPOL_Msk
188#endif
189#ifdef SPI_CFG2_CPOL_Msk
190# define STM32_SPI_CPOL_Msk SPI_CFG2_CPOL_Msk
191#endif
192
200#define HAVE_SPI_MODE_T
201typedef enum {
202 SPI_MODE_0 = 0,
203 SPI_MODE_1 = STM32_SPI_CPHA_Msk,
204 SPI_MODE_2 = STM32_SPI_CPOL_Msk,
205 SPI_MODE_3 = STM32_SPI_CPOL_Msk | STM32_SPI_CPHA_Msk,
206} spi_mode_t;
208
209#endif /* !DOXYGEN */
210
211#ifdef __cplusplus
212}
213#endif
214
bxCAN specific definitions
Backup SRAM CPU specific definitions for the STM32 family.
DMA CPU specific definitions for the STM32 family.
Ethernet CPU specific definitions for the STM32 family.
Specific FMC definitions for the STM32.
GPIO CPU definitions for the STM32 family.
GPIO LL CPU definitions for the STM32 family.
I2C CPU specific definitions for the STM32 family.
LTDC CPU specific definitions for the STM32 family.
PWM CPU specific definitions for the STM32 family.
QDEC CPU specific definitions for the STM32 family.
CPU specific definitions for SDIO/SDMMC for the STM32 family.
SPI CPU specific definitions for the STM32 family.
Timer CPU specific definitions for the STM32 family.
UART CPU specific definitions for the STM32 family.
USB CPU specific definitions for the STM32 family.
CPU internal VBAT interface and definitions of the STM32 family.
Watchdog CPU definitions for the STM32 family.
FDCAN specific definitions.
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:42
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:43
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:45
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:44
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:46
STM32C0 CPU specific definitions for internal peripheral handling.
Common CPU definitions for the STM32 family.
Power Management (PM) CPU specific definitions for the STM32 family.
STM32F0 CPU specific definitions for internal peripheral handling.
STM32F1 CPU specific definitions for internal peripheral handling.
STM32F2 CPU specific definitions for internal peripheral handling.
STM32F3 CPU specific definitions for internal peripheral handling.
STM32F4 CPU specific definitions for internal peripheral handling.
STM32F7 CPU specific definitions for internal peripheral handling.
STM32G0 CPU specific definitions for internal peripheral handling.
STM3G4 CPU specific definitions for internal peripheral handling.
STM32L0 CPU specific definitions for internal peripheral handling.
STM32L1 CPU specific definitions for internal peripheral handling.
STM32L4 CPU specific definitions for internal peripheral handling.
STM32L5 CPU specific definitions for internal peripheral handling.
STM32U5 CPU specific definitions for internal peripheral handling.
STM32WB CPU specific definitions for internal peripheral handling.
STM32WL CPU specific definitions for internal peripheral handling.
ADC device configuration.
Definition periph_cpu.h:377
DAC line configuration data.
Definition periph_cpu.h:300
Unit helper macros.