28#if defined(CPU_FAM_STM32F0)
30#elif defined(CPU_FAM_STM32F1)
32#elif defined(CPU_FAM_STM32F2)
34#elif defined(CPU_FAM_STM32F3)
36#elif defined(CPU_FAM_STM32F4)
38#elif defined(CPU_FAM_STM32F7)
40#elif defined(CPU_FAM_STM32G0)
42#elif defined(CPU_FAM_STM32C0)
44#elif defined(CPU_FAM_STM32G4)
46#elif defined(CPU_FAM_STM32L0)
48#elif defined(CPU_FAM_STM32L1)
50#elif defined(CPU_FAM_STM32L4)
52#elif defined(CPU_FAM_STM32L5)
54#elif defined(CPU_FAM_STM32U5)
56#elif defined(CPU_FAM_STM32WB)
58#elif defined(CPU_FAM_STM32WL)
82#ifdef MODULE_PERIPH_CAN
99#if !defined(CPU_FAM_STM32F0) && !defined(CPU_FAM_STM32L0) && \
100 !defined(CPU_FAM_STM32L1) && !defined(CPU_FAM_STM32WL)
118#define HAVE_PTP_CLOCK_READ 1
119#define HAVE_PTP_CLOCK_SET 1
120#define HAVE_PTP_TIMER_SET_ABSOLUTE 1
129#if defined(USB_OTG_GCCFG_NOVBUSSENS)
130#define STM32_USB_OTG_CID_1x
131#elif defined(USB_OTG_GCCFG_VBDEN)
132#define STM32_USB_OTG_CID_2x
134#define STM32_USB_FS_CID_1x
141#if defined(USB_OTG_FS_MAX_IN_ENDPOINTS)
142#define STM32_USB_OTG_FS_NUM_EP (USB_OTG_FS_MAX_IN_ENDPOINTS)
143#elif defined(STM32_USB_OTG_CID_1x)
144#define STM32_USB_OTG_FS_NUM_EP (4)
145#elif defined(STM32_USB_OTG_CID_2x)
146#define STM32_USB_OTG_FS_NUM_EP (6)
153#if defined(USB_OTG_HS_MAX_IN_ENDPOINTS)
154#define STM32_USB_OTG_HS_NUM_EP (USB_OTG_HS_MAX_IN_ENDPOINTS)
155#elif defined(STM32_USB_OTG_CID_1x)
156#define STM32_USB_OTG_HS_NUM_EP (6)
157#elif defined(STM32_USB_OTG_CID_2x)
158#define STM32_USB_OTG_HS_NUM_EP (9)
171#if defined(MODULE_PERIPH_USBDEV_HS) && defined(STM32_USB_OTG_HS_NUM_EP)
172#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_HS_NUM_EP
173#elif defined(STM32_USB_OTG_FS_NUM_EP)
174#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_FS_NUM_EP
176#define USBDEV_NUM_ENDPOINTS 8
180#ifdef SPI_CR1_CPHA_Msk
181# define STM32_SPI_CPHA_Msk SPI_CR1_CPHA_Msk
183#ifdef SPI_CFG2_CPHA_Msk
184# define STM32_SPI_CPHA_Msk SPI_CFG2_CPHA_Msk
186#ifdef SPI_CR1_CPOL_Msk
187# define STM32_SPI_CPOL_Msk SPI_CR1_CPOL_Msk
189#ifdef SPI_CFG2_CPOL_Msk
190# define STM32_SPI_CPOL_Msk SPI_CFG2_CPOL_Msk
200#define HAVE_SPI_MODE_T
205 SPI_MODE_3 = STM32_SPI_CPOL_Msk | STM32_SPI_CPHA_Msk,
bxCAN specific definitions
Backup SRAM CPU specific definitions for the STM32 family.
DMA CPU specific definitions for the STM32 family.
Ethernet CPU specific definitions for the STM32 family.
Specific FMC definitions for the STM32.
GPIO CPU definitions for the STM32 family.
GPIO LL CPU definitions for the STM32 family.
I2C CPU specific definitions for the STM32 family.
LTDC CPU specific definitions for the STM32 family.
PWM CPU specific definitions for the STM32 family.
QDEC CPU specific definitions for the STM32 family.
CPU specific definitions for SDIO/SDMMC for the STM32 family.
SPI CPU specific definitions for the STM32 family.
Timer CPU specific definitions for the STM32 family.
UART CPU specific definitions for the STM32 family.
USB CPU specific definitions for the STM32 family.
CPU internal VBAT interface and definitions of the STM32 family.
Watchdog CPU definitions for the STM32 family.
FDCAN specific definitions.
spi_mode_t
Support SPI modes.
@ SPI_MODE_0
CPOL=0, CPHA=0.
@ SPI_MODE_2
CPOL=1, CPHA=0.
@ SPI_MODE_1
CPOL=0, CPHA=1.
@ SPI_MODE_3
CPOL=1, CPHA=1.
STM32C0 CPU specific definitions for internal peripheral handling.
Common CPU definitions for the STM32 family.
Power Management (PM) CPU specific definitions for the STM32 family.
STM32F0 CPU specific definitions for internal peripheral handling.
STM32F1 CPU specific definitions for internal peripheral handling.
STM32F2 CPU specific definitions for internal peripheral handling.
STM32F3 CPU specific definitions for internal peripheral handling.
STM32F4 CPU specific definitions for internal peripheral handling.
STM32F7 CPU specific definitions for internal peripheral handling.
STM32G0 CPU specific definitions for internal peripheral handling.
STM3G4 CPU specific definitions for internal peripheral handling.
STM32L0 CPU specific definitions for internal peripheral handling.
STM32L1 CPU specific definitions for internal peripheral handling.
STM32L4 CPU specific definitions for internal peripheral handling.
STM32L5 CPU specific definitions for internal peripheral handling.
STM32U5 CPU specific definitions for internal peripheral handling.
STM32WB CPU specific definitions for internal peripheral handling.
STM32WL CPU specific definitions for internal peripheral handling.
ADC device configuration.
DAC line configuration data.