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periph_cpu.h
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1/*
2 * Copyright (C) 2015-2017 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
21
22#include "kernel_defines.h"
23#include "mutex.h"
24
25#include "cpu.h"
26#include "cpu_conf.h"
27
28#if defined(_SILICON_LABS_32B_SERIES_2)
29#include "em_iadc.h"
30#else
31#include "em_adc.h"
32#endif
33#include "em_cmu.h"
34#include "em_device.h"
35#include "em_gpio.h"
36#include "em_timer.h"
37#include "em_usart.h"
38#include "em_wdog.h"
39#include "em_rtc.h"
40#if defined(_SILICON_LABS_32B_SERIES_0)
41#include "em_dac.h"
42#elif defined (_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2)
43#include "em_vdac.h"
44#endif
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
53typedef struct {
54 CMU_Clock_TypeDef clk;
55 CMU_Select_TypeDef src;
56} clk_mux_t;
57
61typedef struct {
62 CMU_Clock_TypeDef clk;
63 CMU_ClkDiv_TypeDef div;
64} clk_div_t;
65
69#define CPUID_LEN (8U)
70
74#define CLOCK_CORECLOCK SystemCoreClock
75
76#if defined(DAC_COUNT) && DAC_COUNT > 0
80typedef struct {
81 DAC_TypeDef *dev;
82 DAC_Ref_TypeDef ref;
83 CMU_Clock_TypeDef cmu;
85
89typedef struct {
90 uint8_t dev;
91 uint8_t index;
92} dac_chan_conf_t;
93
94#elif defined(VDAC_COUNT) && VDAC_COUNT > 0
98typedef struct {
99 VDAC_TypeDef *dev;
100 VDAC_Ref_TypeDef ref;
101 CMU_Clock_TypeDef cmu;
102} dac_conf_t;
103
107typedef struct {
108 uint8_t dev;
109 uint8_t index;
110} dac_chan_conf_t;
111#endif
112
117/* RTT_MAX_VALUE some are 24bit, some are 32bit */
118#if defined(_RTC_CNT_MASK)
119#define RTT_MAX_VALUE _RTC_CNT_MASK /* mask has all bits set ==> MAX*/
120#elif defined(_RTCC_CNT_MASK)
121#define RTT_MAX_VALUE _RTCC_CNT_MASK /* mask has all bits set ==> MAX*/
122#endif
123#define RTT_MAX_FREQUENCY (32768U) /* in Hz */
124#define RTT_MIN_FREQUENCY (1U) /* in Hz */
125#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz, LFCLK*/
126
128
133#define HAVE_GPIO_T
134typedef uint32_t gpio_t;
136
140#define GPIO_UNDEF (0xffffffff)
141
145#define GPIO_PIN(x, y) ((gpio_t) ((x << 4) | y))
146
150#define GPIO_MODE(x, y) ((x << 1) | y)
151
155enum {
156#if (_GPIO_PORT_A_PIN_COUNT > 0)
157 PA = gpioPortA,
158#endif
159#if (_GPIO_PORT_B_PIN_COUNT > 0)
160 PB = gpioPortB,
161#endif
162#if (_GPIO_PORT_C_PIN_COUNT > 0)
163 PC = gpioPortC,
164#endif
165#if (_GPIO_PORT_D_PIN_COUNT > 0)
166 PD = gpioPortD,
167#endif
168#if (_GPIO_PORT_E_PIN_COUNT > 0)
169 PE = gpioPortE,
170#endif
171#if (_GPIO_PORT_F_PIN_COUNT > 0)
172 PF = gpioPortF,
173#endif
174#if (_GPIO_PORT_G_PIN_COUNT > 0)
175 PG = gpioPortG,
176#endif
177#if (_GPIO_PORT_H_PIN_COUNT > 0)
178 PH = gpioPortH,
179#endif
180#if (_GPIO_PORT_I_PIN_COUNT > 0)
181 PI = gpioPortI,
182#endif
183#if (_GPIO_PORT_J_PIN_COUNT > 0)
184 PJ = gpioPortJ,
185#endif
186#if (_GPIO_PORT_K_PIN_COUNT > 0)
187 PK = gpioPortK
188#endif
189};
190
191#ifndef DOXYGEN
196#define HAVE_GPIO_MODE_T
197typedef enum {
198 GPIO_IN = GPIO_MODE(gpioModeInput, 0),
199 GPIO_IN_PD = GPIO_MODE(gpioModeInputPull, 0),
200 GPIO_IN_PU = GPIO_MODE(gpioModeInputPull, 1),
201 GPIO_OUT = GPIO_MODE(gpioModePushPull, 0),
202 GPIO_OD = GPIO_MODE(gpioModeWiredAnd, 1),
203 GPIO_OD_PU = GPIO_MODE(gpioModeWiredAndPullUp, 1),
206
211#define HAVE_GPIO_FLANK_T
212typedef enum {
213 GPIO_FALLING = 2,
214 GPIO_RISING = 1,
215 GPIO_BOTH = 3
218#endif /* ndef DOXYGEN */
219
220#if defined(_SILICON_LABS_32B_SERIES_2)
228#if defined(_IADC_CFG_DIGAVG_MASK)
229#define ADC_MODE(osr, avg, res) ((osr << 16) | (avg << 8) | res)
230#else
231#define ADC_MODE(osr, res) ((osr << 16) | res)
232#endif
233
237#define ADC_MODE_OSR(mode) ((mode & 0xff0000) >> 16)
238
239#if defined(_IADC_CFG_DIGAVG_MASK)
243#define ADC_MODE_AVG(mode) ((mode & 0x00ff00) >> 8)
244#endif
245
249#define ADC_MODE_RES(mode) ((mode & 0x0000ff) >> 0)
250
255#define HAVE_ADC_RES_T
256#if defined(_IADC_CFG_DIGAVG_MASK)
257typedef enum {
258 ADC_RES_6BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 6),
259 ADC_RES_8BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 8),
260 ADC_RES_10BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 10),
261 ADC_RES_12BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 12),
262 ADC_RES_14BIT = ADC_MODE(iadcCfgOsrHighSpeed8x, iadcDigitalAverage1, 14),
263 ADC_RES_16BIT = ADC_MODE(iadcCfgOsrHighSpeed16x, iadcDigitalAverage2, 16),
264} adc_res_t;
265#else
266typedef enum {
267 ADC_RES_6BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 6),
268 ADC_RES_8BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 8),
269 ADC_RES_10BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 10),
270 ADC_RES_12BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 12),
271 ADC_RES_14BIT = ADC_MODE(iadcCfgOsrHighSpeed8x, 14),
272 ADC_RES_16BIT = ADC_MODE(iadcCfgOsrHighSpeed32x, 16),
273} adc_res_t;
274#endif
275
279typedef struct {
283 IADC_TypeDef *dev;
284
288 CMU_Clock_TypeDef cmu;
289
293 IADC_CfgReference_t reference;
294
300 uint32_t reference_mV;
301
308 IADC_CfgAnalogGain_t gain;
309
317 adc_res_t available_res[IADC0_CONFIGNUM];
318} adc_conf_t;
319
323typedef struct {
327 uint8_t dev;
328
332 gpio_t input_pos;
333
343 gpio_t input_neg;
345#else /* defined(_SILICON_LABS_32B_SERIES_2) */
350#define ADC_MODE(x, y) ((y << 4) | x)
351
355#define ADC_MODE_UNDEF(x) (ADC_MODE(x, 15))
356
357#ifndef DOXYGEN
362#define HAVE_ADC_RES_T
363typedef enum {
364 ADC_RES_6BIT = ADC_MODE(adcRes6Bit, 0),
365 ADC_RES_8BIT = ADC_MODE(adcRes8Bit, 0),
366 ADC_RES_10BIT = ADC_MODE(adcRes12Bit, 2),
367 ADC_RES_12BIT = ADC_MODE(adcRes12Bit, 0),
370} adc_res_t;
372#endif /* ndef DOXYGEN */
373
377typedef struct {
378 ADC_TypeDef *dev;
379 CMU_Clock_TypeDef cmu;
380} adc_conf_t;
381
385typedef struct {
386 uint8_t dev;
387#if defined(_SILICON_LABS_32B_SERIES_0)
388 ADC_SingleInput_TypeDef input;
389#elif defined(_SILICON_LABS_32B_SERIES_1)
390 ADC_PosSel_TypeDef input;
391#endif
392 ADC_Ref_TypeDef reference;
393 ADC_AcqTime_TypeDef acq_time;
395#endif /* !defined(_SILICON_LABS_32B_SERIES_2) */
396
401#define HAVE_HWCRYPTO_AES128
402#ifdef AES_CTRL_AES256
403#define HAVE_HWCRYPTO_AES256
404#endif
405#if defined(_SILICON_LABS_32B_SERIES_1)
406#define HAVE_HWCRYPTO_SHA1
407#define HAVE_HWCRYPTO_SHA256
408#endif
410
411#ifndef DOXYGEN
416#define HAVE_I2C_SPEED_T
417typedef enum {
418 I2C_SPEED_LOW = 10000,
419 I2C_SPEED_NORMAL = 100000,
420 I2C_SPEED_FAST = 400000,
421 I2C_SPEED_FAST_PLUS = 1000000,
422 I2C_SPEED_HIGH = 3400000,
425#endif /* ndef DOXYGEN */
426
430typedef struct {
431 I2C_TypeDef *dev;
432 gpio_t sda_pin;
433 gpio_t scl_pin;
434#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
435 uint32_t loc;
436#endif
437 CMU_Clock_TypeDef cmu;
439 uint32_t speed;
440} i2c_conf_t;
441
446#define PERIPH_I2C_NEED_READ_REG
447#define PERIPH_I2C_NEED_WRITE_REG
449
450#ifndef DOXYGEN
455#define HAVE_PWM_MODE_T
456typedef enum {
457 PWM_LEFT = timerModeUp,
458 PWM_RIGHT = timerModeDown,
459 PWM_CENTER = timerModeUp
460} pwm_mode_t;
462#endif /* ndef DOXYGEN */
463
467typedef struct {
468 uint8_t index;
469 gpio_t pin;
470 uint32_t loc;
472
476typedef struct {
477 TIMER_TypeDef *dev;
478 CMU_Clock_TypeDef cmu;
480 uint8_t channels;
482} pwm_conf_t;
483
484#ifndef DOXYGEN
489#define HAVE_SPI_MODE_T
490typedef enum {
491 SPI_MODE_0 = usartClockMode0,
492 SPI_MODE_1 = usartClockMode1,
493 SPI_MODE_2 = usartClockMode2,
494 SPI_MODE_3 = usartClockMode3
495} spi_mode_t;
497
502#define HAVE_SPI_CLK_T
503typedef enum {
504 SPI_CLK_100KHZ = 100000,
505 SPI_CLK_400KHZ = 400000,
506 SPI_CLK_1MHZ = 1000000,
507 SPI_CLK_5MHZ = 5000000,
508 SPI_CLK_10MHZ = 10000000
509} spi_clk_t;
511#endif /* ndef DOXYGEN */
512
516typedef struct {
517 USART_TypeDef *dev;
518 gpio_t mosi_pin;
519 gpio_t miso_pin;
520 gpio_t clk_pin;
521#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
522 uint32_t loc;
523#endif
524 CMU_Clock_TypeDef cmu;
526} spi_dev_t;
527
532#define PERIPH_SPI_NEEDS_INIT_CS
533#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
534#define PERIPH_SPI_NEEDS_TRANSFER_REG
535#define PERIPH_SPI_NEEDS_TRANSFER_REGS
537
546#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
547typedef struct {
548 void *dev;
549 CMU_Clock_TypeDef cmu;
551#endif
552
553typedef struct {
554#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
559#else
560 void *dev;
561 CMU_Clock_TypeDef cmu;
562 IRQn_Type irq;
563#endif
565
566#define LETIMER_MAX_VALUE _LETIMER_TOP_MASK
567#define TIMER_MAX_VALUE _TIMER_TOP_MASK
569
573#ifndef CONFIG_EFM32_XTIMER_USE_LETIMER
574#define CONFIG_EFM32_XTIMER_USE_LETIMER 0
575#endif
576
580#ifndef DOXYGEN
584#define UART_MODE_UNSUPPORTED 0xf0
585
590#define HAVE_UART_PARITY_T
591#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
592typedef enum {
594 UART_PARITY_ODD = 1,
599#else
600typedef enum {
603 UART_PARITY_ODD = 3,
604 UART_PARITY_MARK = UART_MODE_UNSUPPORTED | 0,
605 UART_PARITY_SPACE = UART_MODE_UNSUPPORTED | 1,
607#endif
609
614#define HAVE_UART_DATA_BITS_T
615#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
616typedef enum {
622#else
623typedef enum {
624 UART_DATA_BITS_5 = UART_MODE_UNSUPPORTED | 0,
625 UART_DATA_BITS_6 = UART_MODE_UNSUPPORTED | 1,
629#endif
631
636#define HAVE_UART_STOP_BITS_T
637#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
638typedef enum {
642#else
643typedef enum {
647#endif
649#endif /* ndef DOXYGEN */
650
651typedef struct {
652 void *dev;
653 gpio_t rx_pin;
654 gpio_t tx_pin;
655#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
656 uint32_t loc;
657#endif
658 CMU_Clock_TypeDef cmu;
661
665#define PROVIDES_PM_OFF
666
670#define PROVIDES_PM_LAYERED_OFF
671
675#define PM_NUM_MODES (3U)
676
681#define EFM32_PM_MODE_EM3 (0U)
682#define EFM32_PM_MODE_EM2 (1U)
683#define EFM32_PM_MODE_EM1 (2U)
685
690#define WDT_CLOCK_HZ (1000U)
691
692#define NWDT_TIME_LOWER_LIMIT ((1U << (3U + wdogPeriod_9)) + 1U)
693#define NWDT_TIME_UPPER_LIMIT ((1U << (3U + wdogPeriod_256k)) + 1U)
694
695#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2)
696#define WDT_TIME_LOWER_LIMIT NWDT_TIME_LOWER_LIMIT
697#define WDT_TIME_UPPER_LIMIT NWDT_TIME_UPPER_LIMIT
698#endif
699
700#define WDT_HAS_STOP (1U)
702
707#define USBDEV_NUM_ENDPOINTS 7
709
710/* GPIO_LL's overrides */
711#ifndef DOXYGEN
712
713/* Not supported by hardware */
714#define HAVE_GPIO_SLEW_T
715typedef enum {
717 GPIO_SLEW_SLOW = 0,
718 GPIO_SLEW_FAST = 0,
721
722/* Not supported by hardware */
723#define HAVE_GPIO_PULL_STRENGTH_T
724typedef enum {
726 GPIO_PULL_WEAK = 0,
730
731/* Not implemented, see gpio_ll_arch.h comments */
732#define HAVE_GPIO_DRIVE_STRENGTH_T
733typedef enum {
735 GPIO_DRIVE_WEAK = 0,
739
740#endif
741
742#ifdef __cplusplus
743}
744#endif
745
gpio_flank_t
Definition periph_cpu.h:179
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:164
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:163
i2c_speed_t
Definition periph_cpu.h:275
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition periph_cpu.h:279
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition periph_cpu.h:276
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition periph_cpu.h:281
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:278
spi_clk_t
Definition periph_cpu.h:351
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:356
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:355
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:353
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:354
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:352
pwm_mode_t
@ PWM_CENTER
center aligned
@ PWM_LEFT
left aligned
@ PWM_RIGHT
right aligned
Implementation specific CPU configuration options.
#define GPIO_MODE(x, y)
Internal macro for combining pin mode (x) and pull-up/down (y).
Definition periph_cpu.h:150
#define ADC_MODE(x, y)
Internal macro for combining ADC resolution (x) with number of shifts (y).
Definition periph_cpu.h:350
#define ADC_MODE_UNDEF(x)
Internal define to note that resolution is not supported.
Definition periph_cpu.h:355
enum IRQn IRQn_Type
Interrupt Number Definition.
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:91
adc_res_t
Possible ADC resolution settings.
Definition adc.h:92
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition adc.h:98
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition adc.h:94
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition adc.h:97
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition adc.h:93
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition adc.h:95
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition adc.h:96
gpio_pull_strength_t
Enumeration of pull resistor values.
Definition gpio_ll.h:275
gpio_slew_t
Enumeration of slew rate settings.
Definition gpio_ll.h:339
gpio_drive_strength_t
Enumeration of drive strength options.
Definition gpio_ll.h:306
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
Definition gpio_ll.h:276
@ GPIO_PULL_WEAK
Use a weak pull resistor.
Definition gpio_ll.h:277
@ GPIO_PULL_STRONG
Use a strong pull resistor.
Definition gpio_ll.h:278
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
Definition gpio_ll.h:279
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
Definition gpio_ll.h:340
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
Definition gpio_ll.h:343
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
Definition gpio_ll.h:342
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
Definition gpio_ll.h:344
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
Definition gpio_ll.h:309
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
Definition gpio_ll.h:308
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
Definition gpio_ll.h:310
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
Definition gpio_ll.h:307
Common macros and compiler attributes/pragmas configuration.
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:42
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:43
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:45
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:44
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:46
Mutex for thread synchronization.
uart_parity_t
Definition of possible parity modes.
Definition periph_cpu.h:501
@ UART_PARITY_SPACE
space parity
Definition periph_cpu.h:506
@ UART_PARITY_NONE
no parity
Definition periph_cpu.h:502
@ UART_PARITY_EVEN
even parity
Definition periph_cpu.h:503
@ UART_PARITY_ODD
odd parity
Definition periph_cpu.h:504
@ UART_PARITY_MARK
mark parity
Definition periph_cpu.h:505
uart_stop_bits_t
Definition of possible stop bits lengths.
Definition periph_cpu.h:533
@ UART_STOP_BITS_2
2 stop bits
Definition periph_cpu.h:535
@ UART_STOP_BITS_1
1 stop bit
Definition periph_cpu.h:534
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition periph_cpu.h:517
@ UART_DATA_BITS_6
6 data bits
Definition periph_cpu.h:519
@ UART_DATA_BITS_5
5 data bits
Definition periph_cpu.h:518
@ UART_DATA_BITS_7
7 data bits
Definition periph_cpu.h:520
@ UART_DATA_BITS_8
8 data bits
Definition periph_cpu.h:521
@ PB
port B
@ PC
port C
@ PA
port A
@ PD
port D
ADC channel configuration.
Definition periph_cpu.h:385
ADC_AcqTime_TypeDef acq_time
channel acquisition time
Definition periph_cpu.h:393
uint8_t dev
device index
Definition periph_cpu.h:386
ADC_Ref_TypeDef reference
channel voltage reference
Definition periph_cpu.h:392
ADC device configuration.
Definition periph_cpu.h:377
ADC_TypeDef * dev
ADC device used.
Definition periph_cpu.h:378
CMU_Clock_TypeDef cmu
the device CMU channel
Definition periph_cpu.h:379
Clock divider configuration.
Definition periph_cpu.h:61
CMU_ClkDiv_TypeDef div
Divisor.
Definition periph_cpu.h:63
CMU_Clock_TypeDef clk
Clock domain.
Definition periph_cpu.h:62
Clock mux configuration.
Definition periph_cpu.h:53
CMU_Select_TypeDef src
Source clock.
Definition periph_cpu.h:55
CMU_Clock_TypeDef clk
Clock domain.
Definition periph_cpu.h:54
DAC line configuration data.
Definition periph_cpu.h:300
I2C configuration structure.
Definition periph_cpu.h:298
i2c_speed_t speed
Configured bus speed, actual speed may be lower but never higher.
Definition periph_cpu.h:303
CMU_Clock_TypeDef cmu
the device CMU channel
Definition periph_cpu.h:437
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:299
IRQn_Type irq
the devices base IRQ channel
Definition periph_cpu.h:438
gpio_t sda_pin
SDA GPIO pin.
Definition periph_cpu.h:301
gpio_t scl_pin
SCL GPIO pin.
Definition periph_cpu.h:302
PWM channel configuration.
Definition periph_cpu.h:467
uint32_t loc
location of the pin
Definition periph_cpu.h:470
uint8_t index
TIMER channel to use.
Definition periph_cpu.h:468
gpio_t pin
pin used for pwm
Definition periph_cpu.h:469
PWM device configuration.
IRQn_Type irq
the devices base IRQ channel
Definition periph_cpu.h:479
const pwm_chan_conf_t * channel
pointer to first channel config
Definition periph_cpu.h:481
CMU_Clock_TypeDef cmu
the device CMU channel
Definition periph_cpu.h:478
uint8_t channels
the number of available channels
Definition periph_cpu.h:480
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:516
gpio_t clk_pin
pin used for CLK
Definition periph_cpu.h:520
gpio_t mosi_pin
pin used for MOSI
Definition periph_cpu.h:518
USART_TypeDef * dev
USART device used.
Definition periph_cpu.h:517
CMU_Clock_TypeDef cmu
the device CMU channel
Definition periph_cpu.h:524
IRQn_Type irq
the devices base IRQ channel
Definition periph_cpu.h:525
gpio_t miso_pin
pin used for MISO
Definition periph_cpu.h:519
Timer device configuration.
Definition periph_cpu.h:263
IRQn_Type irq
number of the higher timer IRQ channel
Definition periph_cpu.h:557
timer_dev_t prescaler
the lower neighboring timer (not initialized for LETIMER)
Definition periph_cpu.h:555
timer_dev_t timer
the higher numbered timer
Definition periph_cpu.h:556
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:264
uint8_t channel_numof
number of channels per timer
Definition periph_cpu.h:558
Define timer configuration values.
Definition periph_cpu.h:547
void * dev
TIMER_TypeDef or LETIMER_TypeDef device used.
Definition periph_cpu.h:548
CMU_Clock_TypeDef cmu
the device CMU channel
Definition periph_cpu.h:549
UART device configuration.
Definition periph_cpu.h:217
CMU_Clock_TypeDef cmu
the device CMU channel
Definition periph_cpu.h:658
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:218
IRQn_Type irq
the devices base IRQ channel
Definition periph_cpu.h:659
uint32_t loc
location of UART pins
Definition periph_cpu.h:656
gpio_t tx_pin
pin used for TX
Definition periph_cpu.h:221
gpio_t rx_pin
pin used for RX
Definition periph_cpu.h:220