periph_cpu.h

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/*
 * Copyright (C) 2020 iosabi
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#pragma once

 
#include <stdint.h>
#include <stdbool.h>
 
#include "cpu.h"
 
#ifdef __cplusplus
extern "C" {
#endif

#define HAVE_GPIO_T
typedef uint16_t gpio_t;

#define GPIO_UNDEF          (0xffff)

#define GPIO_PIN(x, y)      (((x) << 12u) | (y))
 
/* QN908x has a unique default Bluetooth address in the Flash Information Page
 * descriptor. This value is set in the factory and cannot be modified by
 * users. However, the actual Bluetooth address used by the stack may be
 * different, this is just the default. */
#define CPUID_ADDR          (FSL_FEATURE_FLASH_ADDR_OF_VENDOR_BD_ADDR)

#define CPUID_LEN           (6U)

#define WDT_HAS_STOP        (1)

#define NWDT_TIME_LOWER_LIMIT (1U)
#define NWDT_TIME_UPPER_LIMIT (268435U)
#define WWDT_TIME_LOWER_LIMIT (1U)
#define WWDT_TIME_UPPER_LIMIT (268435U)

#define GPIO_MODE(open_drain, out_enabled, pull_mode) \
    ((open_drain) | ((out_enabled) << 1) | ((pull_mode) << 4))
 
#ifndef DOXYGEN
#define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN     = GPIO_MODE(0, 0, 0),       
    GPIO_IN_PD  = GPIO_MODE(0, 0, 1),       
    GPIO_IN_PU  = GPIO_MODE(0, 0, 2),       
    GPIO_OUT    = GPIO_MODE(0, 1, 0),       
    GPIO_OD     = GPIO_MODE(1, 1, 0),       
    GPIO_OD_PU  = GPIO_MODE(1, 1, 2),       
} gpio_mode_t;
#endif /* ndef DOXYGEN */
 
#ifndef DOXYGEN
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_LOW        = 0,    
    GPIO_HIGH       = 1,    
    GPIO_RISING     = 2,    
    GPIO_FALLING    = 3,    
    GPIO_BOTH       = 4,    
} gpio_flank_t;
#endif /* ndef DOXYGEN */

enum {
    PORT_A  = 0,            
    PORT_B  = 1,            
    GPIO_PORTS_NUMOF        
};
 
#if DOXYGEN
#define BOARD_HAS_ADC_PA06_CAP
#endif
 
#ifndef DOXYGEN
#define HAVE_ADC_RES_T
typedef enum {
    ADC_RES_6BIT = 6u,         
    ADC_RES_8BIT = 8u,         
    ADC_RES_10BIT = 10u,       
    ADC_RES_12BIT = 12u,       
    ADC_RES_14BIT = 14u,       
    ADC_RES_16BIT = 16u,       
    /* Extra modes supported by this CPU. */
    ADC_RES_MAX = 22u,         
    ADC_RES_UV = 23u,          
} adc_res_t;
#endif /* ifndef DOXYGEN */

typedef enum {
    ADC_CLOCK_4M,     
    ADC_CLOCK_2M,     
    ADC_CLOCK_1M,     
    ADC_CLOCK_500K,   
    ADC_CLOCK_250K,   
    ADC_CLOCK_125K,   
    ADC_CLOCK_62K5,   
    ADC_CLOCK_31K25,  
    ADC_CLOCK_32K,    
} qn908x_adc_clock_t;
 
#ifdef DOXYGEN
#define QN908X_ADC_CLOCK
#endif /* ifdef DOXYGEN */

typedef enum {
    ADC_CHANNEL_ADC0_ADC1 =  0u << 9u,   
    ADC_CHANNEL_ADC2_ADC3 =  1u << 9u,   
    ADC_CHANNEL_ADC4_ADC5 =  2u << 9u,   
    ADC_CHANNEL_ADC6_ADC7 =  3u << 9u,   
    ADC_CHANNEL_ADC0_VINN =  4u << 9u,   
    ADC_CHANNEL_ADC1_VINN =  5u << 9u,   
    ADC_CHANNEL_ADC2_VINN =  6u << 9u,   
    ADC_CHANNEL_ADC3_VINN =  7u << 9u,   
    ADC_CHANNEL_ADC4_VINN =  8u << 9u,   
    ADC_CHANNEL_ADC5_VINN =  9u << 9u,   
    ADC_CHANNEL_ADC6_VINN = 10u << 9u,   
    ADC_CHANNEL_ADC7_VINN = 11u << 9u,   
    ADC_CHANNEL_TEMP      = 13u << 9u,   
    ADC_CHANNEL_VCC4_VINN = 14u << 9u,   
    ADC_CHANNEL_VINN_VINN = 15u << 9u,   
    ADC_CHANNEL_VINN_VSS  = 20u << 9u,   
} qn908x_adc_channel_t;

typedef enum {
    ADC_VREF_1V2  = 0x0000u, 
    ADC_VREF_VREF = 0x4000u, 
    ADC_VREF_VEXT = 0x8000u, 
    ADC_VREF_VCC  = 0xC000u, 
} qn908x_adc_vref_t;

#define ADC_VREF_GAIN_X15 (0x100u)

#define ADC_PGA_ENABLE (0x08u)

typedef enum {
    ADC_VINN_VREF     = 0x30u, 
    ADC_VINN_VREF_3_4 = 0x20u, 
    ADC_VINN_VREF_2   = 0x10u, 
    ADC_VINN_AVSS     = 0x00u, 
} qn908x_adc_vinn_t;

typedef enum {
    ADC_GAIN_X05 = 0x40u, 
    ADC_GAIN_X1  = 0x00u, 
    ADC_GAIN_X15 = 0xC0u, 
    ADC_GAIN_X20 = 0x80u, 
} qn908x_adc_gain_t;

typedef uint16_t adc_conf_t;

#define TIMER_CHANNEL_NUMOF (4)
#define TIMER_MAX_VALUE     (0xffffffff)
#define PERIPH_TIMER_PROVIDES_SET   1

#define HAVE_I2C_SPEED_T
typedef enum {
    I2C_SPEED_LOW       = 10000u,   
    I2C_SPEED_NORMAL    = 100000u,  
    I2C_SPEED_FAST      = 400000u,  
    I2C_SPEED_FAST_PLUS = 400000u,  
    I2C_SPEED_HIGH      = 400000u,  
} i2c_speed_t;


typedef struct {
    I2C_Type *dev;          
    gpio_t pin_scl;         
    gpio_t pin_sda;         
    uint32_t speed;         
} i2c_conf_t;

#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_WRITE_REGS

#define i2c_pin_sda(dev) i2c_config[dev].pin_sda
#define i2c_pin_scl(dev) i2c_config[dev].pin_scl

#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
 
#ifndef DOXYGEN
#define SPI_HWCS(x)         (1u << 15u | (x))

#define SPI_HWCS_NUMOF 4

#define SPI_MODE_SEL(pol, pha)          (SPI_CFG_CPOL(pol) | SPI_CFG_CPHA(pha))

#define HAVE_SPI_MODE_T
typedef enum {
    SPI_MODE_0  = SPI_MODE_SEL(0, 0),   
    SPI_MODE_1  = SPI_MODE_SEL(0, 1),   
    SPI_MODE_2  = SPI_MODE_SEL(1, 0),   
    SPI_MODE_3  = SPI_MODE_SEL(1, 1)    
} spi_mode_t;

#define HAVE_SPI_CLK_T
typedef enum {
    SPI_CLK_100KHZ  =   100000u,    
    SPI_CLK_400KHZ  =   400000u,    
    SPI_CLK_1MHZ    =  1000000u,    
    SPI_CLK_5MHZ    =  5000000u,    
    SPI_CLK_10MHZ   = 10000000u     
} spi_clk_t;

#define spi_pin_mosi(bus) spi_config[bus].copi_pin
#define spi_pin_miso(bus) spi_config[bus].cipo_pin
#define spi_pin_clk(bus)  spi_config[bus].clk_pin

typedef struct {
    SPI_Type *dev;                   
    gpio_t cipo_pin;                 
    gpio_t copi_pin;                 
    gpio_t clk_pin;                  
    gpio_t cs_pin[SPI_HWCS_NUMOF];   
} spi_conf_t;
 
#endif /* ifndef DOXYGEN */

typedef struct {
    USART_Type *dev;    
    gpio_t rx_pin;      
    gpio_t tx_pin;      
} uart_conf_t;

#define UART_INVALID_MODE   (0x80)

typedef enum {
    UART_PARITY_NONE = 0,                         
    UART_PARITY_EVEN = 2,                         
    UART_PARITY_ODD = 3,                          
    UART_PARITY_MARK = 0x10 | UART_INVALID_MODE,  
    UART_PARITY_SPACE = 0x20 | UART_INVALID_MODE, 
} uart_parity_t;
#define HAVE_UART_PARITY_T

typedef enum {
    UART_DATA_BITS_5 = 0x10 | UART_INVALID_MODE, 
    UART_DATA_BITS_6 = 0x20 | UART_INVALID_MODE, 
    UART_DATA_BITS_7 = 0,                        
    UART_DATA_BITS_8 = 1,                        
    /* Note: There's a UART_DATA_BITS_9 possible in this hardware. */
} uart_data_bits_t;
#define HAVE_UART_DATA_BITS_T

typedef enum {
    UART_STOP_BITS_1    = 0,    
    UART_STOP_BITS_2    = 1,    
} uart_stop_bits_t;
#define HAVE_UART_STOP_BITS_T
 
#ifdef __cplusplus
}
#endif