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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2020 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#include "periph_cpu.h"
20#include "cfg_clock_32_1.h"
21#include "cfg_rtt_default.h"
22#include "cfg_timer_default.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
32static const uart_conf_t uart_config[] = {
33 {
34 .dev = NRF_UARTE0,
35 .rx_pin = GPIO_PIN(1, 10),
36 .tx_pin = GPIO_PIN(1, 3),
37#ifdef MODULE_PERIPH_UART_HW_FC
38 .rts_pin = GPIO_UNDEF,
39 .cts_pin = GPIO_UNDEF,
40#endif
41 .irqn = UARTE0_UART0_IRQn,
42 },
43};
44
45#define UART_0_ISR (isr_uart0)
46
47#define UART_NUMOF ARRAY_SIZE(uart_config)
49
54static const i2c_conf_t i2c_config[] = {
55 {
56 .dev = NRF_TWIM0,
57 .scl = GPIO_PIN(0, 2),
58 .sda = GPIO_PIN(0, 31),
59 .speed = I2C_SPEED_NORMAL
60 },
61};
62
63#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
65
70static const spi_conf_t spi_config[] = {
71 {
72 .dev = NRF_SPIM0,
73 .sclk = GPIO_PIN(0, 13),
74 .mosi = GPIO_PIN(1, 1),
75 .miso = GPIO_PIN(1, 8),
76 }
77};
78
79#define SPI_NUMOF ARRAY_SIZE(spi_config)
81
82#ifdef __cplusplus
83}
84#endif
85
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:274
Common clock configuration for the nRF52 based boards.
I2C configuration structure.
Definition periph_cpu.h:295
SPI device configuration.
Definition periph_cpu.h:333
UART device configuration.
Definition periph_cpu.h:214