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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2018 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
19#include "cfg_clock_16_1.h"
20#include "cfg_timer_012.h"
21#include "cfg_rtt_default.h"
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
31static const uart_conf_t uart_config[] = {
32 { /* Mapped to USB virtual COM port */
33 .dev = NRF_UART0,
34 .rx_pin = GPIO_PIN(0, 11),
35 .tx_pin = GPIO_PIN(0, 9),
36#ifdef MODULE_PERIPH_UART_HW_FC
37 .rts_pin = GPIO_PIN(0, 8),
38 .cts_pin = GPIO_PIN(0, 10),
39#endif
40 .irqn = UART0_IRQn,
41 },
42};
43
44#define UART_NUMOF ARRAY_SIZE(uart_config)
45#define UART_0_ISR isr_uart0
47
52static const spi_conf_t spi_config[] = {
53 {
54 .dev = NRF_SPI0,
55 .sclk = 29,
56 .mosi = 25,
57 .miso = 28
58 }
59};
60
61#define SPI_NUMOF ARRAY_SIZE(spi_config)
63
68static const i2c_conf_t i2c_config[] = {
69 {
70 .dev = NRF_TWI1,
71 .pin_scl = 7,
72 .pin_sda = 30,
73 .ppi = 0,
74 .speed = I2C_SPEED_NORMAL
75 }
76};
77
78#define I2C_NUMOF ARRAY_SIZE(i2c_config)
80
100static const adc_conf_t adc_config[] = {2, 3, 4, 5, 6, 7};
101
102#define ADC_NUMOF ARRAY_SIZE(adc_config)
104
105#ifdef __cplusplus
106}
107#endif
108
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:274
Common clock configuration for some nrf51 based boards.
Shared timer peripheral configuration mapping timers 0, 1, and 2.
@ UART0_IRQn
UART0.
Definition cc2538.h:49
ADC device configuration.
Definition periph_cpu.h:374
I2C configuration structure.
Definition periph_cpu.h:295
SPI device configuration.
Definition periph_cpu.h:333
UART device configuration.
Definition periph_cpu.h:214