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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2016 OTA keys
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
19#include "clk_conf.h"
20#include "cfg_timer_tim2.h"
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
30static const uart_conf_t uart_config[] = {
31 {
32 .dev = USART2,
33 .rcc_mask = RCC_APB1ENR_USART2EN,
34 .rx_pin = GPIO_PIN(PORT_A, 15),
35 .tx_pin = GPIO_PIN(PORT_A, 2),
36 .rx_af = GPIO_AF1,
37 .tx_af = GPIO_AF1,
38 .bus = APB1,
39 .irqn = USART2_IRQn
40 },
41 {
42 .dev = USART1,
43 .rcc_mask = RCC_APB2ENR_USART1EN,
44 .rx_pin = GPIO_PIN(PORT_A, 10),
45 .tx_pin = GPIO_PIN(PORT_A, 9),
46 .rx_af = GPIO_AF1,
47 .tx_af = GPIO_AF1,
48 .bus = APB2,
49 .irqn = USART1_IRQn
50 }
51};
52
53#define UART_0_ISR (isr_usart2)
54#define UART_1_ISR (isr_usart1)
55
56#define UART_NUMOF ARRAY_SIZE(uart_config)
58
63static const pwm_conf_t pwm_config[] = {
64 {
65 .dev = TIM1,
66 .rcc_mask = RCC_APB2ENR_TIM1EN,
67 .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
68 { .pin = GPIO_UNDEF, .cc_chan = 0 },
69 { .pin = GPIO_UNDEF, .cc_chan = 0 },
70 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
71 .af = GPIO_AF2,
72 .bus = APB2
73 },
74 {
75 .dev = TIM14,
76 .rcc_mask = RCC_APB1ENR_TIM14EN,
77 .chan = { { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 0 },
78 { .pin = GPIO_UNDEF, .cc_chan = 0 },
79 { .pin = GPIO_UNDEF, .cc_chan = 0 },
80 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
81 .af = GPIO_AF0,
82 .bus = APB1
83 },
84 {
85 .dev = TIM3,
86 .rcc_mask = RCC_APB1ENR_TIM3EN,
87 .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
88 { .pin = GPIO_UNDEF, .cc_chan = 0 },
89 { .pin = GPIO_UNDEF, .cc_chan = 0 },
90 { .pin = GPIO_UNDEF, .cc_chan = 0 }},
91 .af = GPIO_AF1,
92 .bus = APB1
93 }
94};
95
96#define PWM_NUMOF ARRAY_SIZE(pwm_config)
98
103static const spi_conf_t spi_config[] = {
104 {
105 .dev = SPI1,
106 .mosi_pin = GPIO_PIN(PORT_B, 5),
107 .miso_pin = GPIO_PIN(PORT_B, 4),
108 .sclk_pin = GPIO_PIN(PORT_B, 3),
109 .cs_pin = SPI_CS_UNDEF,
110 .mosi_af = GPIO_AF0,
111 .miso_af = GPIO_AF0,
112 .sclk_af = GPIO_AF0,
113 .cs_af = GPIO_AF0,
114 .rccmask = RCC_APB2ENR_SPI1EN,
115 .apbbus = APB2
116 }
117};
118
119#define SPI_NUMOF ARRAY_SIZE(spi_config)
121
126static const adc_conf_t adc_config[] = {
127 { GPIO_PIN(PORT_A, 0), 0 },
128 { GPIO_PIN(PORT_A, 1), 1 },
129 { GPIO_PIN(PORT_A, 3), 3 },
130 { GPIO_PIN(PORT_A, 4), 4 },
131 { GPIO_PIN(PORT_A, 7), 7 },
132 { GPIO_UNDEF, 18 }, /* VBAT */
133};
134
135#define VBAT_ADC ADC_LINE(5)
136#define ADC_NUMOF ARRAY_SIZE(adc_config)
138
139#ifdef __cplusplus
140}
141#endif
142
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_A
port A
Definition periph_cpu.h:43
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:101
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:374
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
UART device configuration.
Definition periph_cpu.h:214