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periph_conf.h
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1/*
2 * Copyright (C) 2015 TriaGnoSys GmbH
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
20
21/* This board provides an LSE */
22#ifndef CONFIG_BOARD_HAS_LSE
23#define CONFIG_BOARD_HAS_LSE 1
24#endif
25
26/* This board provides an HSE */
27#ifndef CONFIG_BOARD_HAS_HSE
28#define CONFIG_BOARD_HAS_HSE 1
29#endif
30
31#include "periph_cpu.h"
32#include "clk_conf.h"
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
42static const timer_conf_t timer_config[] = {
43 {
44 .dev = TIM2,
45 .max = 0x0000ffff,
46 .rcc_mask = RCC_APB1ENR_TIM2EN,
47 .bus = APB1,
48 .irqn = TIM2_IRQn
49 },
50 {
51 .dev = TIM3,
52 .max = 0x0000ffff,
53 .rcc_mask = RCC_APB1ENR_TIM3EN,
54 .bus = APB1,
55 .irqn = TIM3_IRQn
56 }
57};
58
59#define TIMER_0_ISR isr_tim2
60#define TIMER_1_ISR isr_tim3
61
62#define TIMER_NUMOF ARRAY_SIZE(timer_config)
64
69static const uart_conf_t uart_config[] = {
70 {
71 .dev = USART2,
72 .rcc_mask = RCC_APB1ENR_USART2EN,
73 .rx_pin = GPIO_PIN(PORT_A, 3),
74 .tx_pin = GPIO_PIN(PORT_A, 2),
75 .bus = APB1,
76 .irqn = USART2_IRQn
77 },
78 {
79 .dev = USART1,
80 .rcc_mask = RCC_APB2ENR_USART1EN,
81 .rx_pin = GPIO_PIN(PORT_A, 10),
82 .tx_pin = GPIO_PIN(PORT_A, 9),
83 .bus = APB2,
84 .irqn = USART1_IRQn
85 },
86 {
87 .dev = USART3,
88 .rcc_mask = RCC_APB1ENR_USART3EN,
89 .rx_pin = GPIO_PIN(PORT_B, 11),
90 .tx_pin = GPIO_PIN(PORT_B, 10),
91 .bus = APB1,
92 .irqn = USART3_IRQn
93 }
94};
95
96#define UART_0_ISR (isr_usart2)
97#define UART_1_ISR (isr_usart1)
98#define UART_2_ISR (isr_usart3)
99
100#define UART_NUMOF ARRAY_SIZE(uart_config)
102
107#ifndef RTT_FREQUENCY
108#define RTT_FREQUENCY (16384) /* in Hz */
109#endif
111
117static const i2c_conf_t i2c_config[] = {
118 {
119 .dev = I2C1,
120 .speed = I2C_SPEED_NORMAL,
121 .scl_pin = GPIO_PIN(PORT_B, 8),
122 .sda_pin = GPIO_PIN(PORT_B, 9),
123 .bus = APB1,
124 .rcc_mask = RCC_APB1ENR_I2C1EN,
125 .clk = CLOCK_APB1,
126 .irqn = I2C1_EV_IRQn
127 },
128 {
129 .dev = I2C2,
130 .speed = I2C_SPEED_NORMAL,
131 .scl_pin = GPIO_PIN(PORT_B, 10),
132 .sda_pin = GPIO_PIN(PORT_B, 11),
133 .bus = APB1,
134 .rcc_mask = RCC_APB1ENR_I2C2EN,
135 .clk = CLOCK_APB1,
136 .irqn = I2C2_EV_IRQn
137 }
138};
139
140#define I2C_0_ISR isr_i2c1_ev
141#define I2C_1_ISR isr_i2c2_ev
142
143#define I2C_NUMOF ARRAY_SIZE(i2c_config)
145
150static const spi_conf_t spi_config[] = {
151 {
152 .dev = SPI1,
153 .mosi_pin = GPIO_PIN(PORT_A, 7),
154 .miso_pin = GPIO_PIN(PORT_A, 6),
155 .sclk_pin = GPIO_PIN(PORT_A, 5),
156 .cs_pin = SPI_CS_UNDEF,
157 .rccmask = RCC_APB2ENR_SPI1EN,
158 .apbbus = APB2
159 },
160 {
161 .dev = SPI2,
162 .mosi_pin = GPIO_PIN(PORT_B, 15),
163 .miso_pin = GPIO_PIN(PORT_B, 14),
164 .sclk_pin = GPIO_PIN(PORT_B, 13),
165 .cs_pin = SPI_CS_UNDEF,
166 .rccmask = RCC_APB1ENR_SPI2EN,
167 .apbbus = APB1
168 }
169};
170
171#define SPI_NUMOF ARRAY_SIZE(spi_config)
173
178static const adc_conf_t adc_config[] = {
179 { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 0 }, /* ADC12_IN0 */
180 { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 1 }, /* ADC12_IN1 */
181 { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 4 }, /* ADC12_IN4 */
182 { .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 8 }, /* ADC12_IN8 */
183 { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 11 }, /* ADC12_IN11 */
184 { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 10 }, /* ADC12_IN10 */
185};
186
187#define ADC_NUMOF ARRAY_SIZE(adc_config)
189
190#ifdef __cplusplus
191}
192#endif
193
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
I2C configuration structure.
Definition periph_cpu.h:298
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
Definition periph_cpu.h:263
UART device configuration.
Definition periph_cpu.h:217