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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2015 Freie Universität Berlin
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19/* This board provides an LSE */
20#ifndef CONFIG_BOARD_HAS_LSE
21#define CONFIG_BOARD_HAS_LSE 1
22#endif
23
24/* This board provides an HSE */
25#ifndef CONFIG_BOARD_HAS_HSE
26#define CONFIG_BOARD_HAS_HSE 1
27#endif
28
29#include "periph_cpu.h"
30#include "clk_conf.h"
31#include "cfg_timer_tim2.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
47static const adc_conf_t adc_config[] = {
48 { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 1 }, /* ADC1_IN1, fast */
49 { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 2 }, /* ADC1_IN2, fast */
50 { .pin = GPIO_PIN(PORT_A, 4), .dev = 1, .chan = 1 }, /* ADC2_IN1, fast */
51 { .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 11 }, /* ADC1_IN11, slow */
52 { .pin = GPIO_PIN(PORT_C, 1), .dev = 1, .chan = 7 }, /* ADC12_IN7, slow */
53 { .pin = GPIO_PIN(PORT_C, 0), .dev = 1, .chan = 6 }, /* ADC12_IN6, slow */
54 { .pin = GPIO_UNDEF, .dev = 0, .chan = 17 }, /* VBAT */
55};
56
57#define VBAT_ADC ADC_LINE(6)
58#define ADC_NUMOF ARRAY_SIZE(adc_config)
60
65static const dma_conf_t dma_config[] = {
66 { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX | USART3_TX */
67 { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
68 { .stream = 3 }, /* DMA1 Channel 4 - USART1_TX */
69 { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
70};
71
72#define DMA_0_ISR isr_dma1_channel2
73#define DMA_1_ISR isr_dma1_channel3
74#define DMA_2_ISR isr_dma1_channel4
75#define DMA_3_ISR isr_dma1_channel7
76#define DMA_NUMOF ARRAY_SIZE(dma_config)
78
83static const uart_conf_t uart_config[] = {
84 {
85 .dev = USART2,
86 .rcc_mask = RCC_APB1ENR_USART2EN,
87 .rx_pin = GPIO_PIN(PORT_A, 3),
88 .tx_pin = GPIO_PIN(PORT_A, 2),
89 .rx_af = GPIO_AF7,
90 .tx_af = GPIO_AF7,
91 .bus = APB1,
92 .irqn = USART2_IRQn,
93#ifdef MODULE_PERIPH_DMA
94 .dma = 3,
96#endif
97 },
98 {
99 .dev = USART1,
100 .rcc_mask = RCC_APB2ENR_USART1EN,
101 .rx_pin = GPIO_PIN(PORT_A, 10),
102 .tx_pin = GPIO_PIN(PORT_A, 9),
103 .rx_af = GPIO_AF7,
104 .tx_af = GPIO_AF7,
105 .bus = APB2,
106 .irqn = USART1_IRQn,
107#ifdef MODULE_PERIPH_DMA
108 .dma = 2,
110#endif
111 },
112/* SPI1 RX and USART3 are sharing the same DMA channel, so disable the
113 * third UART when both SPI and DMA features are enabled. */
114#if !defined(MODULE_PERIPH_SPI) || !defined(MODULE_PERIPH_DMA)
115 {
116 .dev = USART3,
117 .rcc_mask = RCC_APB1ENR_USART3EN,
118 .rx_pin = GPIO_PIN(PORT_B, 11),
119 .tx_pin = GPIO_PIN(PORT_B, 10),
120 .rx_af = GPIO_AF7,
121 .tx_af = GPIO_AF7,
122 .bus = APB1,
123 .irqn = USART3_IRQn,
124#ifdef MODULE_PERIPH_DMA
125 .dma = 0,
127#endif
128 }
129#endif /* !defined(MODULE_PERIPH_SPI) || !defined(MODULE_PERIPH_DMA) */
130};
131
132#define UART_0_ISR (isr_usart2)
133#define UART_1_ISR (isr_usart1)
134#define UART_2_ISR (isr_usart3)
135
136#define UART_NUMOF ARRAY_SIZE(uart_config)
138
143static const pwm_conf_t pwm_config[] = {
144 {
145 .dev = TIM3,
146 .rcc_mask = RCC_APB1ENR_TIM3EN,
147 .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
148 { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
149 { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
150 { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
151 .af = GPIO_AF2,
152 .bus = APB1
153 }
154};
155
156#define PWM_NUMOF ARRAY_SIZE(pwm_config)
158
163static const spi_conf_t spi_config[] = {
164 {
165 .dev = SPI1,
166 .mosi_pin = GPIO_PIN(PORT_A, 7),
167 .miso_pin = GPIO_PIN(PORT_A, 6),
168 .sclk_pin = GPIO_PIN(PORT_A, 5),
169 .cs_pin = GPIO_UNDEF,
170 .mosi_af = GPIO_AF5,
171 .miso_af = GPIO_AF5,
172 .sclk_af = GPIO_AF5,
173 .cs_af = GPIO_AF5,
174 .rccmask = RCC_APB2ENR_SPI1EN,
175 .apbbus = APB2,
176#ifdef MODULE_PERIPH_DMA
177 .tx_dma = 1,
178 .tx_dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED,
179 .rx_dma = 0,
180 .rx_dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
181#endif
182 }
183};
184
185#define SPI_NUMOF ARRAY_SIZE(spi_config)
187
188#ifdef __cplusplus
189}
190#endif
191
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_A
port A
Definition periph_cpu.h:43
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 Timer peripheral based on TIM2.
#define DMA_CHAN_CONFIG_UNSUPPORTED
DMA channel/trigger configuration for DMA peripherals without channel/trigger filtering such as the s...
Definition cpu_dma.h:95
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:374
DMA configuration.
Definition cpu_dma.h:31
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
UART device configuration.
Definition periph_cpu.h:214