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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28#include "periph_cpu.h"
29#include "clk_conf.h"
30#include "cfg_i2c1_pb8_pb9.h"
31#include "cfg_rtt_default.h"
32#include "cfg_timer_tim2.h"
33#include "cfg_usb_otg_fs.h"
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
43static const uart_conf_t uart_config[] = {
44 {
45 .dev = USART3,
46 .rcc_mask = RCC_APB1ENR_USART3EN,
47 .rx_pin = GPIO_PIN(PORT_D, 9),
48 .tx_pin = GPIO_PIN(PORT_D, 8),
49 .rx_af = GPIO_AF7,
50 .tx_af = GPIO_AF7,
51 .bus = APB1,
52 .irqn = USART3_IRQn,
53#ifdef UART_USE_DMA
54 .dma_stream = 6,
55 .dma_chan = 4
56#endif
57 },
58 {
59 .dev = USART6,
60 .rcc_mask = RCC_APB2ENR_USART6EN,
61 .rx_pin = GPIO_PIN(PORT_G, 9),
62 .tx_pin = GPIO_PIN(PORT_G, 14),
63 .rx_af = GPIO_AF8,
64 .tx_af = GPIO_AF8,
65 .bus = APB2,
66 .irqn = USART6_IRQn,
67#ifdef UART_USE_DMA
68 .dma_stream = 5,
69 .dma_chan = 4
70#endif
71 },
72 {
73 .dev = USART2,
74 .rcc_mask = RCC_APB1ENR_USART2EN,
75 .rx_pin = GPIO_PIN(PORT_D, 6),
76 .tx_pin = GPIO_PIN(PORT_D, 5),
77 .rx_af = GPIO_AF7,
78 .tx_af = GPIO_AF7,
79 .bus = APB1,
80 .irqn = USART2_IRQn,
81#ifdef UART_USE_DMA
82 .dma_stream = 4,
83 .dma_chan = 4
84#endif
85 }
86};
87
88#define UART_0_ISR (isr_usart3)
89#define UART_0_DMA_ISR (isr_dma1_stream6)
90#define UART_1_ISR (isr_usart6)
91#define UART_1_DMA_ISR (isr_dma1_stream5)
92#define UART_2_ISR (isr_usart2)
93#define UART_2_DMA_ISR (isr_dma1_stream4)
94
95#define UART_NUMOF ARRAY_SIZE(uart_config)
97
98static const adc_conf_t adc_config[] = {
99 {GPIO_PIN(PORT_A, 3), .dev = 2, .chan = 3}, /* ADC123_IN3 */
100 {GPIO_PIN(PORT_C, 0), .dev = 2, .chan = 10}, /* ADC123_IN10 */
101 {GPIO_PIN(PORT_C, 3), .dev = 2, .chan = 13}, /* ADC123_IN13 */
102 {GPIO_PIN(PORT_F, 3), .dev = 2, .chan = 9}, /* ADC3_IN9 */
103 {GPIO_PIN(PORT_F, 5), .dev = 2, .chan = 15}, /* ADC3_IN15 */
104 {GPIO_PIN(PORT_F, 10), .dev = 2, .chan = 8}, /* ADC3_IN8 */
105 {GPIO_UNDEF, .dev = 0, .chan = 18}, /* VBAT */
106};
107
108#define VBAT_ADC ADC_LINE(6)
109
110#define ADC_CLK_MAX MHZ(36)
111
112#define ADC_NUMOF ARRAY_SIZE(adc_config)
113
114#ifdef __cplusplus
115}
116#endif
117
@ PORT_G
port G
Definition periph_cpu.h:49
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_F
port F
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:43
@ PORT_D
port D
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:374
UART device configuration.
Definition periph_cpu.h:214