Loading...
Searching...
No Matches
periph_conf.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2017 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28#include "periph_cpu.h"
29#include "clk_conf.h"
30#include "cfg_i2c1_pb8_pb9.h"
31#include "cfg_rtt_default.h"
32#include "cfg_timer_tim2.h"
33#include "cfg_usb_otg_fs.h"
34#include "mii.h"
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
44static const dma_conf_t dma_config[] = {
45 { .stream = 4 }, /* DMA1 Stream 4 - USART3_TX */
46 { .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
47 { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
48 { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
49};
50
51#define DMA_0_ISR isr_dma1_stream4
52#define DMA_1_ISR isr_dma2_stream6
53#define DMA_2_ISR isr_dma1_stream6
54#define DMA_3_ISR isr_dma2_stream0
55
56#define DMA_NUMOF ARRAY_SIZE(dma_config)
58
63static const uart_conf_t uart_config[] = {
64 {
65 .dev = USART3,
66 .rcc_mask = RCC_APB1ENR_USART3EN,
67 .rx_pin = GPIO_PIN(PORT_D, 9),
68 .tx_pin = GPIO_PIN(PORT_D, 8),
69 .rx_af = GPIO_AF7,
70 .tx_af = GPIO_AF7,
71 .bus = APB1,
72 .irqn = USART3_IRQn,
73#ifdef MODULE_PERIPH_DMA
74 .dma = 0,
75 .dma_chan = 7
76#endif
77 },
78 {
79 .dev = USART6,
80 .rcc_mask = RCC_APB2ENR_USART6EN,
81 .rx_pin = GPIO_PIN(PORT_G, 9),
82 .tx_pin = GPIO_PIN(PORT_G, 14),
83 .rx_af = GPIO_AF8,
84 .tx_af = GPIO_AF8,
85 .bus = APB2,
86 .irqn = USART6_IRQn,
87#ifdef MODULE_PERIPH_DMA
88 .dma = 1,
89 .dma_chan = 5
90#endif
91 },
92 {
93 .dev = USART2,
94 .rcc_mask = RCC_APB1ENR_USART2EN,
95 .rx_pin = GPIO_PIN(PORT_D, 6),
96 .tx_pin = GPIO_PIN(PORT_D, 5),
97 .rx_af = GPIO_AF7,
98 .tx_af = GPIO_AF7,
99 .bus = APB1,
100 .irqn = USART2_IRQn,
101#ifdef MODULE_PERIPH_DMA
102 .dma = 2,
103 .dma_chan = 4
104#endif
105 }
106};
107
108#define UART_0_ISR (isr_usart3)
109#define UART_1_ISR (isr_usart6)
110#define UART_2_ISR (isr_usart2)
111
112#define UART_NUMOF ARRAY_SIZE(uart_config)
114
119static const spi_conf_t spi_config[] = {
120 {
121 .dev = SPI1,
122 /* PA7 is the default MOSI pin, as it is required for compatibility with
123 * Arduino(ish) shields. Sadly, it is also connected to the RMII_DV of
124 * Ethernet PHY. We work around this by remapping the MOSI to PB5 when
125 * the on-board Ethernet PHY is used.
126 */
127#ifdef MODULE_PERIPH_ETH
128 .mosi_pin = GPIO_PIN(PORT_B, 5),
129#else
130 .mosi_pin = GPIO_PIN(PORT_A, 7),
131#endif
132 .miso_pin = GPIO_PIN(PORT_A, 6),
133 .sclk_pin = GPIO_PIN(PORT_A, 5),
134 .cs_pin = SPI_CS_UNDEF,
135 .mosi_af = GPIO_AF5,
136 .miso_af = GPIO_AF5,
137 .sclk_af = GPIO_AF5,
138 .cs_af = GPIO_AF5,
139 .rccmask = RCC_APB2ENR_SPI1EN,
140 .apbbus = APB2
141 },
142 {
143 .dev = SPI4,
144 .mosi_pin = GPIO_PIN(PORT_E, 6),
145 .miso_pin = GPIO_PIN(PORT_E, 5),
146 .sclk_pin = GPIO_PIN(PORT_E, 2),
147 .cs_pin = SPI_CS_UNDEF,
148 .mosi_af = GPIO_AF5,
149 .miso_af = GPIO_AF5,
150 .sclk_af = GPIO_AF5,
151 .cs_af = GPIO_AF5,
152 .rccmask = RCC_APB2ENR_SPI4EN,
153 .apbbus = APB2
154 }
155};
156
157#define SPI_NUMOF ARRAY_SIZE(spi_config)
159
164static const eth_conf_t eth_config = {
165 .mode = RMII,
167 .dma = 3,
168 .dma_chan = 8,
169 .phy_addr = 0x00,
170 .pins = {
171 GPIO_PIN(PORT_G, 13),
172 GPIO_PIN(PORT_B, 13),
173 GPIO_PIN(PORT_G, 11),
174 GPIO_PIN(PORT_C, 4),
175 GPIO_PIN(PORT_C, 5),
176 GPIO_PIN(PORT_A, 7),
177 GPIO_PIN(PORT_C, 1),
178 GPIO_PIN(PORT_A, 2),
179 GPIO_PIN(PORT_A, 1),
180 }
181};
182
183#define ETH_DMA_ISR isr_dma2_stream0
185
196static const adc_conf_t adc_config[] = {
197 {GPIO_PIN(PORT_A, 3), 2, 3},
198 {GPIO_PIN(PORT_C, 0), 2, 10},
199 {GPIO_PIN(PORT_C, 3), 2, 13},
200 {GPIO_PIN(PORT_F, 3), 2, 9},
201 {GPIO_PIN(PORT_F, 5), 2, 15},
202 {GPIO_PIN(PORT_F, 10), 2, 8},
203 {GPIO_UNDEF, 0, 18}, /* VBAT */
204};
205
206#define VBAT_ADC ADC_LINE(6)
207#define ADC_CLK_MAX MHZ(36)
208#define ADC_NUMOF ARRAY_SIZE(adc_config)
210
218static const pwm_conf_t pwm_config[] = {
219 {
220 .dev = TIM1,
221 .rcc_mask = RCC_APB2ENR_TIM1EN,
222 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 CN10-4 */, .cc_chan = 0},
223 { .pin = GPIO_PIN(PORT_E, 11) /* D5 CN10-6 */, .cc_chan = 1},
224 { .pin = GPIO_PIN(PORT_E, 13) /* D3 CN10-10 */, .cc_chan = 2},
225 { .pin = GPIO_PIN(PORT_E, 14) /* D38 CN10-28 */, .cc_chan = 3} },
226 .af = GPIO_AF1,
227 .bus = APB2
228 },
229 {
230 .dev = TIM4,
231 .rcc_mask = RCC_APB1ENR_TIM4EN,
232 .chan = { { .pin = GPIO_PIN(PORT_D, 12) /* D29 CN10-21 */, .cc_chan = 0},
233 { .pin = GPIO_PIN(PORT_D, 13) /* D28 CN10-19 */, .cc_chan = 1},
234 { .pin = GPIO_PIN(PORT_D, 14) /* D10 CN7-16 */, .cc_chan = 2},
235 { .pin = GPIO_PIN(PORT_D, 15) /* D9 CN7-18 */, .cc_chan = 3} },
236 .af = GPIO_AF2,
237 .bus = APB1
238 },
239};
240
244#define PWM_NUMOF ARRAY_SIZE(pwm_config)
246
247#ifdef __cplusplus
248}
249#endif
250
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_G
port G
Definition periph_cpu.h:49
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_F
port F
Definition periph_cpu.h:48
@ PORT_E
port E
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:43
@ PORT_D
port D
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
Definition cpu_eth.h:36
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
#define MII_BMCR_FULL_DPLX
Set for full duplex.
Definition mii.h:68
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Definition mii.h:72
Interface definition for MII/RMII h.
ADC device configuration.
Definition periph_cpu.h:374
DMA configuration.
Definition cpu_dma.h:31
Ethernet Peripheral configuration.
Definition cpu_eth.h:43
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
UART device configuration.
Definition periph_cpu.h:214