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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2017 Inria
4 * SPDX-FileCopyrightText: 2017 HAW-Hamburg
5 * SPDX-License-Identifier: LGPL-2.1-only
6 */
7
8#pragma once
9
21
22/* Add specific clock configuration (HSE, LSE) for this board here */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27#include "periph_cpu.h"
28#include "clk_conf.h"
29#include "cfg_i2c1_pb8_pb9.h"
30#include "cfg_rtt_default.h"
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
40static const dma_conf_t dma_config[] = {
41 { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX | USART3_TX */
42 { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
43 { .stream = 3 }, /* DMA1 Channel 4 - USART1_TX */
44 { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
45};
46
47#define DMA_0_ISR isr_dma1_channel2
48#define DMA_1_ISR isr_dma1_channel3
49#define DMA_2_ISR isr_dma1_channel4
50#define DMA_3_ISR isr_dma1_channel7
51
52#define DMA_NUMOF ARRAY_SIZE(dma_config)
54
59static const timer_conf_t timer_config[] = {
60 {
61 .dev = TIM5,
62 .max = 0xffffffff,
63 .rcc_mask = RCC_APB1ENR1_TIM5EN,
64 .bus = APB1,
65 .irqn = TIM5_IRQn
66 }
67};
68
69#define TIMER_0_ISR isr_tim5
70
71#define TIMER_NUMOF ARRAY_SIZE(timer_config)
73
78static const uart_conf_t uart_config[] = {
79 {
80 .dev = USART2,
81 .rcc_mask = RCC_APB1ENR1_USART2EN,
82 .rx_pin = GPIO_PIN(PORT_A, 3),
83 .tx_pin = GPIO_PIN(PORT_A, 2),
84 .rx_af = GPIO_AF7,
85 .tx_af = GPIO_AF7,
86 .bus = APB1,
87 .irqn = USART2_IRQn,
88 .type = STM32_USART,
89 .clk_src = 0, /* Use APB clock */
90#ifdef MODULE_PERIPH_DMA
91 .dma = 3,
92 .dma_chan = 2
93#endif
94 },
95 {
96 .dev = USART3,
97 .rcc_mask = RCC_APB1ENR1_USART3EN,
98 .rx_pin = GPIO_PIN(PORT_C, 11),
99 .tx_pin = GPIO_PIN(PORT_C, 10),
100 .rx_af = GPIO_AF7,
101 .tx_af = GPIO_AF7,
102 .bus = APB1,
103 .irqn = USART3_IRQn,
104 .type = STM32_USART,
105 .clk_src = 0, /* Use APB clock */
106#ifdef MODULE_PERIPH_DMA
107 .dma = 0,
108 .dma_chan = 2
109#endif
110 },
111 {
112 .dev = USART1,
113 .rcc_mask = RCC_APB2ENR_USART1EN,
114 .rx_pin = GPIO_PIN(PORT_A, 10),
115 .tx_pin = GPIO_PIN(PORT_A, 9),
116 .rx_af = GPIO_AF7,
117 .tx_af = GPIO_AF7,
118 .bus = APB2,
119 .irqn = USART1_IRQn,
120 .type = STM32_USART,
121 .clk_src = 0, /* Use APB clock */
122#ifdef MODULE_PERIPH_DMA
123 .dma = 2,
124 .dma_chan = 2
125#endif
126 }
127};
128
129#define UART_0_ISR (isr_usart2)
130#define UART_1_ISR (isr_usart3)
131#define UART_2_ISR (isr_usart1)
132
133#define UART_NUMOF ARRAY_SIZE(uart_config)
135
140static const pwm_conf_t pwm_config[] = {
141 {
142 .dev = TIM2,
143 .rcc_mask = RCC_APB1ENR1_TIM2EN,
144 .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
145 { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
146 { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
147 { .pin = GPIO_PIN(PORT_B, 11), .cc_chan = 3} },
148 .af = GPIO_AF1,
149 .bus = APB1
150 },
151 {
152 .dev = TIM3,
153 .rcc_mask = RCC_APB1ENR1_TIM3EN,
154 .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
155 { .pin = GPIO_UNDEF, .cc_chan = 0 },
156 { .pin = GPIO_UNDEF, .cc_chan = 0 },
157 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
158 .af = GPIO_AF2,
159 .bus = APB1
160 },
161 {
162 .dev = TIM8,
163 .rcc_mask = RCC_APB2ENR_TIM8EN,
164 .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
165 { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
166 { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
167 { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
168 .af = GPIO_AF3,
169 .bus = APB2
170 }
171};
172
173#define PWM_NUMOF ARRAY_SIZE(pwm_config)
175
180static const spi_conf_t spi_config[] = {
181 {
182 .dev = SPI1,
183 .mosi_pin = GPIO_PIN(PORT_A, 7),
184 .miso_pin = GPIO_PIN(PORT_A, 6),
185 .sclk_pin = GPIO_PIN(PORT_A, 5),
186 .cs_pin = SPI_CS_UNDEF,
187 .mosi_af = GPIO_AF5,
188 .miso_af = GPIO_AF5,
189 .sclk_af = GPIO_AF5,
190 .cs_af = GPIO_AF5,
191 .rccmask = RCC_APB2ENR_SPI1EN,
192 .apbbus = APB2,
193#ifdef MODULE_PERIPH_DMA
194 .tx_dma = 1,
195 .tx_dma_chan = 1,
196 .rx_dma = 0,
197 .rx_dma_chan = 1,
198#endif
199 }
200};
201
202#define SPI_NUMOF ARRAY_SIZE(spi_config)
204
233static const adc_conf_t adc_config[] = {
234 {GPIO_PIN(PORT_A, 0), 0, 5}, /*< ADC12_IN5 */
235 {GPIO_PIN(PORT_A, 1), 0, 6}, /*< ADC12_IN6 */
236 {GPIO_PIN(PORT_A, 4), 1, 9}, /*< ADC12_IN9 */
237 {GPIO_PIN(PORT_B, 0), 1, 15}, /*< ADC12_IN15 */
238 {GPIO_PIN(PORT_C, 1), 2, 2}, /*< ADC123_IN2 */
239 {GPIO_PIN(PORT_C, 0), 2, 1}, /*< ADC123_IN1 */
240 {GPIO_UNDEF, 0, 18}, /* VBAT */
241};
242
243#define VBAT_ADC ADC_LINE(6)
244#define ADC_NUMOF ARRAY_SIZE(adc_config)
246
247#ifdef __cplusplus
248}
249#endif
250
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_A
port A
Definition periph_cpu.h:43
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF3
use alternate function 3
Definition cpu_gpio.h:104
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:374
DMA configuration.
Definition cpu_dma.h:31
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
Timer device configuration.
Definition periph_cpu.h:260
UART device configuration.
Definition periph_cpu.h:214