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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* Add specific clock configuration (HSE, LSE) for this board here */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23#include "periph_cpu.h"
24#include "clk_conf.h"
25#include "cfg_i2c1_pb8_pb9.h"
26#include "cfg_rtt_default.h"
27#include "cfg_usb_otg_fs.h"
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
37static const timer_conf_t timer_config[] = {
38 {
39 .dev = TIM2,
40 .max = 0xffffffff,
41 .rcc_mask = RCC_APB1ENR1_TIM2EN,
42 .bus = APB1,
43 .irqn = TIM2_IRQn
44 },
45 {
46 .dev = TIM5,
47 .max = 0xffffffff,
48 .rcc_mask = RCC_APB1ENR1_TIM5EN,
49 .bus = APB1,
50 .irqn = TIM5_IRQn
51 },
52};
53
54#define TIMER_0_ISR isr_tim2
55#define TIMER_1_ISR isr_tim5
56
57#define TIMER_NUMOF ARRAY_SIZE(timer_config)
59
64static const uart_conf_t uart_config[] = {
65 {
66 .dev = LPUART1,
67 .rcc_mask = RCC_APB1ENR2_LPUART1EN,
68 .rx_pin = GPIO_PIN(PORT_G, 8),
69 .tx_pin = GPIO_PIN(PORT_G, 7),
70 .rx_af = GPIO_AF8,
71 .tx_af = GPIO_AF8,
72 .bus = APB12,
73 .irqn = LPUART1_IRQn,
74 .type = STM32_LPUART,
75 .clk_src = 0,
76 },
77 {
78 .dev = USART3,
79 .rcc_mask = RCC_APB1ENR1_USART3EN,
80 .rx_pin = GPIO_PIN(PORT_D, 9),
81 .tx_pin = GPIO_PIN(PORT_D, 8),
82 .rx_af = GPIO_AF7,
83 .tx_af = GPIO_AF7,
84 .bus = APB1,
85 .irqn = USART3_IRQn,
86 .type = STM32_USART,
87 .clk_src = 0, /* Use APB clock */
88#ifdef UART_USE_DMA
89 .dma_stream = 5,
90 .dma_chan = 4
91#endif
92 }
93};
94
95#define UART_0_ISR (isr_lpuart1)
96#define UART_1_ISR (isr_usart3)
97#define UART_1_DMA_ISR (isr_dma1_stream5)
98
99#define UART_NUMOF ARRAY_SIZE(uart_config)
101
106static const pwm_conf_t pwm_config[] = {
107 {
108 .dev = TIM1,
109 .rcc_mask = RCC_APB2ENR_TIM1EN,
110 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
111 { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
112 { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
113 { .pin = GPIO_UNDEF, .cc_chan = 0} },
114 .af = GPIO_AF1,
115 .bus = APB2
116 },
117 {
118 .dev = TIM4,
119 .rcc_mask = RCC_APB1ENR1_TIM4EN,
120 .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
121 { .pin = GPIO_UNDEF, .cc_chan = 0},
122 { .pin = GPIO_UNDEF, .cc_chan = 0},
123 { .pin = GPIO_UNDEF, .cc_chan = 0} },
124 .af = GPIO_AF2,
125 .bus = APB1
126 },
127};
128
129#define PWM_NUMOF ARRAY_SIZE(pwm_config)
131
136static const spi_conf_t spi_config[] = {
137 {
138 .dev = SPI1,
139 .mosi_pin = GPIO_PIN(PORT_A, 7),
140 .miso_pin = GPIO_PIN(PORT_A, 6),
141 .sclk_pin = GPIO_PIN(PORT_A, 5),
142 .cs_pin = SPI_CS_UNDEF,
143 .mosi_af = GPIO_AF5,
144 .miso_af = GPIO_AF5,
145 .sclk_af = GPIO_AF5,
146 .cs_af = GPIO_AF5,
147 .rccmask = RCC_APB2ENR_SPI1EN,
148 .apbbus = APB2
149 }
150};
151
152#define SPI_NUMOF ARRAY_SIZE(spi_config)
154
183static const adc_conf_t adc_config[] = {
184 { .pin = GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 8 }, /* ADC12_IN8 */
185 { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 1 }, /* ADC123_IN1 */
186 { .pin = GPIO_PIN(PORT_C, 3), .dev = 0, .chan = 4 }, /* ADC123_IN4 */
187 { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 2 }, /* ADC123_IN2 */
188 { .pin = GPIO_PIN(PORT_C, 4), .dev = 0, .chan = 13 }, /* ADC12_IN13 */
189 { .pin = GPIO_PIN(PORT_C, 5), .dev = 0, .chan = 14 }, /* ADC12_IN14 */
190 { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 },
191};
192
196#define ADC_NUMOF ARRAY_SIZE(adc_config)
197
201#define VBAT_ADC ADC_LINE(6)
202
204
205#ifdef __cplusplus
206}
207#endif
208
@ PORT_G
port G
Definition periph_cpu.h:49
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_E
port E
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:43
@ PORT_D
port D
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:38
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:374
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
Timer device configuration.
Definition periph_cpu.h:260
UART device configuration.
Definition periph_cpu.h:214