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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2015-2020 Freie Universität Berlin
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#include "cpu.h"
20#include "periph_cpu.h"
21#include "em_cmu.h"
22#include "usbdev_cfg_otg_fs.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
32#ifndef CLOCK_HF
33#define CLOCK_HF cmuSelect_HFXO
34#endif
35#ifndef CLOCK_CORE_DIV
36#define CLOCK_CORE_DIV cmuClkDiv_1
37#endif
38#ifndef CLOCK_LFA
39#define CLOCK_LFA cmuSelect_LFXO
40#endif
41#ifndef CLOCK_LFB
42#define CLOCK_LFB cmuSelect_LFXO
43#endif
44#ifndef CLOCK_LFE
45#define CLOCK_LFE cmuSelect_LFXO
46#endif
48
53static const adc_conf_t adc_config[] = {
54 {
55 .dev = ADC0,
56 .cmu = cmuClock_ADC0,
57 }
58};
59
60static const adc_chan_conf_t adc_channel_config[] = {
61 {
62 .dev = 0,
63 .input = adcPosSelTEMP,
64 .reference = adcRef1V25,
65 .acq_time = adcAcqTime8
66 },
67 {
68 .dev = 0,
69 .input = adcPosSelAVDD,
70 .reference = adcRef5V,
71 .acq_time = adcAcqTime8
72 }
73};
74
75#define ADC_DEV_NUMOF ARRAY_SIZE(adc_config)
76#define ADC_NUMOF ARRAY_SIZE(adc_channel_config)
78
83static const dac_conf_t dac_config[] = {
84 {
85 .dev = VDAC0,
86 .ref = vdacRefAvdd,
87 .cmu = cmuClock_VDAC0,
88 },
89};
90
91static const dac_chan_conf_t dac_channel_config[] = {
92 {
93 .dev = 0,
94 .index = 0,
95 },
96};
97
98#define DAC_DEV_NUMOF ARRAY_SIZE(dac_config)
99#define DAC_NUMOF ARRAY_SIZE(dac_channel_config)
101
106static const i2c_conf_t i2c_config[] = {
107 {
108 .dev = I2C0,
109 .sda_pin = GPIO_PIN(PE, 4),
110 .scl_pin = GPIO_PIN(PE, 5),
111 .loc = I2C_ROUTELOC0_SDALOC_LOC7 |
112 I2C_ROUTELOC0_SCLLOC_LOC7,
113 .cmu = cmuClock_I2C0,
114 .irq = I2C0_IRQn,
115 .speed = I2C_SPEED_NORMAL
116 }
117};
118
119#define I2C_NUMOF ARRAY_SIZE(i2c_config)
120#define I2C_0_ISR isr_i2c0
122
127#ifndef RTT_FREQUENCY
128#define RTT_FREQUENCY (1U) /* in Hz */
129#endif
131
136static const spi_dev_t spi_config[] = {
137 {
138 .dev = USART3,
139 .mosi_pin = GPIO_PIN(PA, 0),
140 .miso_pin = GPIO_PIN(PA, 1),
141 .clk_pin = GPIO_PIN(PA, 2),
142 .loc = USART_ROUTELOC0_RXLOC_LOC0 |
143 USART_ROUTELOC0_TXLOC_LOC0 |
144 USART_ROUTELOC0_CLKLOC_LOC0,
145 .cmu = cmuClock_USART3,
146 .irq = USART3_RX_IRQn
147 }
148};
149
150#define SPI_NUMOF ARRAY_SIZE(spi_config)
152
159static const timer_conf_t timer_config[] = {
160 {
161 .prescaler = {
162 .dev = TIMER0,
163 .cmu = cmuClock_TIMER0
164 },
165 .timer = {
166 .dev = TIMER1,
167 .cmu = cmuClock_TIMER1
168 },
169 .irq = TIMER1_IRQn,
170 .channel_numof = 3
171 },
172 {
173 .prescaler = {
174 .dev = NULL,
175 .cmu = cmuClock_LETIMER0
176 },
177 .timer = {
178 .dev = LETIMER0,
179 .cmu = cmuClock_LETIMER0
180 },
181 .irq = LETIMER0_IRQn,
182 .channel_numof = 2
183 }
184};
185
186#define TIMER_NUMOF ARRAY_SIZE(timer_config)
187#define TIMER_0_ISR isr_timer1
188#define TIMER_1_ISR isr_letimer0
190
195static const uart_conf_t uart_config[] = {
196 {
197 .dev = USART0,
198 .rx_pin = GPIO_PIN(PE, 6),
199 .tx_pin = GPIO_PIN(PE, 7),
200 .loc = USART_ROUTELOC0_RXLOC_LOC1 |
201 USART_ROUTELOC0_TXLOC_LOC1,
202 .cmu = cmuClock_USART0,
203 .irq = USART0_RX_IRQn
204 },
205 {
206 .dev = UART0,
207 .rx_pin = GPIO_PIN(PC, 5),
208 .tx_pin = GPIO_PIN(PC, 4),
209 .loc = UART_ROUTELOC0_RXLOC_LOC4 |
210 UART_ROUTELOC0_TXLOC_LOC4,
211 .cmu = cmuClock_UART0,
212 .irq = UART0_RX_IRQn
213 }
214};
215
216#define UART_NUMOF ARRAY_SIZE(uart_config)
217#define UART_0_ISR_RX isr_usart0_rx
218#define UART_1_ISR_RX isr_uart0_rx
220
221#ifdef __cplusplus
222}
223#endif
224
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:274
#define UART0
UART0 register bank.
@ PC
port C
@ PA
port A
ADC channel configuration.
Definition periph_cpu.h:382
ADC device configuration.
Definition periph_cpu.h:374
DAC line configuration data.
Definition periph_cpu.h:300
I2C configuration structure.
Definition periph_cpu.h:295
SPI device configuration.
Definition periph_cpu.h:513
Timer device configuration.
Definition periph_cpu.h:260
UART device configuration.
Definition periph_cpu.h:214
Common configuration for EFM32 OTG FS peripheral.