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periph_cpu.h
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1/*
2 * Copyright (C) 2015 Freie Universität Berlin
3 * 2015 Hamburg University of Applied Sciences
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
10#pragma once
11
23
24#include "periph_cpu_common.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
34#define PERIPH_SPI_NEEDS_INIT_CS
35#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
36#define PERIPH_SPI_NEEDS_TRANSFER_REG
37#define PERIPH_SPI_NEEDS_TRANSFER_REGS
39
43#define CPUID_LEN (16U)
44
49#define RTT_MAX_VALUE (0xffffffff)
50#define RTT_CLOCK_FREQUENCY (CHIP_FREQ_XTAL_32K) /* in Hz */
51#define RTT_MIN_FREQUENCY (1) /* in Hz */
52#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
54
62#define ADC_NUMOF (16U)
63
75#define DAC_NUMOF (2U)
76
77#ifndef DOXYGEN
82#define HAVE_SPI_MODE_T
83typedef enum {
84 SPI_MODE_0 = (SPI_CSR_NCPHA),
85 SPI_MODE_1 = (0),
86 SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA),
87 SPI_MODE_3 = (SPI_CSR_CPOL)
90
95#define HAVE_SPI_CLK_T
96typedef enum {
97 SPI_CLK_100KHZ = (100000),
98 SPI_CLK_400KHZ = (400000),
99 SPI_CLK_1MHZ = (1000000),
100 SPI_CLK_5MHZ = (5000000),
101 SPI_CLK_10MHZ = (10000000)
102} spi_clk_t;
104#endif /* ndef DOXYGEN */
105
106#ifndef DOXYGEN
111#define HAVE_ADC_RES_T
112typedef enum {
113 ADC_RES_6BIT = 0x1,
114 ADC_RES_8BIT = 0x2,
115 ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10,
116 ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12,
117 ADC_RES_14BIT = 0x4,
118 ADC_RES_16BIT = 0x8
119} adc_res_t;
121#endif /* ndef DOXYGEN */
122
126typedef struct {
127 gpio_t pin;
128 uint8_t hwchan;
130
134typedef struct {
135 Spi *dev;
136 uint8_t id;
137 gpio_t clk;
138 gpio_t mosi;
139 gpio_t miso;
141} spi_conf_t;
142
143#ifdef __cplusplus
144}
145#endif
146
spi_clk_t
Definition periph_cpu.h:348
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:353
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:352
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:350
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:351
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:349
adc_res_t
Possible ADC resolution settings.
Definition adc.h:92
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition adc.h:98
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition adc.h:94
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition adc.h:97
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition adc.h:93
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition adc.h:95
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition adc.h:96
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:42
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:43
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:45
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:44
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:46
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
PWM channel configuration.
Definition periph_cpu.h:464
uint8_t hwchan
the HW channel used for a logical channel
Definition periph_cpu.h:128
SPI device configuration.
Definition periph_cpu.h:333
gpio_mux_t mux
pin MUX setting
Definition periph_cpu.h:140
uint8_t id
corresponding ID of that module
Definition periph_cpu.h:136
gpio_t mosi
GPIO used as MOSI pin.
Definition periph_cpu.h:863
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:334
unsigned long clk
pin used for SCK
Definition periph_cpu.h:136
gpio_t miso
GPIO used as MISO pin.
Definition periph_cpu.h:864